PIC18F4450-I/P Microchip Technology, PIC18F4450-I/P Datasheet
PIC18F4450-I/P
Specifications of PIC18F4450-I/P
Available stocks
Related parts for PIC18F4450-I/P
PIC18F4450-I/P Summary of contents
Page 1
... Microchip Technology Inc. PIC18F2450/4450 28/40/44-Pin High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology Preliminary Data Sheet DS39760C ...
Page 2
... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 3
... Program Memory Device Flash # Single-Word (bytes) Instructions PIC18F2450 16K 8192 PIC18F4450 16K 8192 * Includes 256 bytes of dual access RAM used by USB module and shared with data memory. © 2007 Microchip Technology Inc. PIC18F2450/4450 Peripheral Highlights: • High-Current Sink/Source: 25 mA/25 mA • Three External Interrupts • ...
Page 4
... REF RA4/T0CKI/RCV RA5/AN4/HLVDIN V OSC1/CLKI OSC2/CLKO/RA6 Note: Pinouts are subject to change. DS39760C-page 2 /RE3 REF REF USB RB3/AN9/VPO + 2 20 RB2/AN8/INT2/VMO 3 19 RB1/AN10/INT1 PIC18F2450 4 RB0/AN12/INT0 RC7/RX/ Preliminary RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0 RB3/AN9/VPO RB2/AN8/INT2/VMO RB1/AN10/INT1 RB0/AN12/INT0 RC7/RX/DT RC6/TX/CK RC5/D+/VP RC4/D-/ © 2007 Microchip Technology Inc. ...
Page 5
... Pinouts are subject to change. © 2007 Microchip Technology Inc. PIC18F2450/4450 1 RB7/KBI3/PGD 40 RB6/KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0 37 + RB3/AN9/VPO 5 36 RB2/AN8/INT2/VMO RB1/AN10/INT1 34 8 RB0/AN12/INT0 RD7 RD6 29 RD5 13 28 RD4 14 27 RC7/RX/ RC6/TX/ RC5/D+/ RC4/D-/VM 23 RD3 RD2 PIC18F4450 Preliminary DD SS OSC2/CLKO/RA6 OSC1/CLKI RE2/AN7 RE1/AN6 RE0/AN5 RA5/AN4/HLVDIN RA4/T0CKI/RCV DS39760C-page 3 ...
Page 6
... RD6 RD7 RB0/AN12/INT0 RB1/AN10/INT1 RB2/AN8/INT2/VMO RB3/AN9/VPO Note: Pinouts are subject to change. * Assignment of this feature is dependent on device configuration. DS39760C-page 4 NC/ICRST*/ICV 1 33 RC0/T1OSO/T1CKI 2 32 OSC2/CLKO/RA6 31 3 OSC1/CLKI PIC18F4450 RE2/AN7 27 7 RE1/AN6 8 26 RE0/AN5 9 25 RA5/AN4/HLVDIN RA4/T0CKI/RCV 11 Preliminary * PP © 2007 Microchip Technology Inc. ...
Page 7
... Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 307 Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 307 Index ................................................................................................................................................................................................. 309 The Microchip Web Site ..................................................................................................................................................................... 317 Customer Change Notification Service .............................................................................................................................................. 317 Customer Support .............................................................................................................................................................................. 317 Reader Response .............................................................................................................................................................................. 318 PIC18F2450/4450 Product Identification System .............................................................................................................................. 319 © 2007 Microchip Technology Inc. PIC18F2450/4450 Preliminary DS39760C-page 5 ...
Page 8
... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39760C-page 6 Preliminary © 2007 Microchip Technology Inc. ...
Page 9
... DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC18F2450 • PIC18F4450 This family of devices offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price – with the addi- tion of high-endurance, Enhanced Flash program memory ...
Page 10
... Standard devices with Enhanced Flash memory, designated with an “F” in the part number (such as PIC18F2450), accommodate an operating V range of 4.2V to 5.5V. Low-voltage parts, DD designated by “LF” (such as PIC18LF2450), function over an extended V range of 2.0V to 5.5V. DD Preliminary © 2007 Microchip Technology Inc. ...
Page 11
... Stack Underflow (PWRT, OST), Stack Underflow (PWRT, OST), MCLR (optional), WDT Yes Yes 75 Instructions; 83 with Extended Instruction Set 83 with Extended Instruction Set enabled 28-Pin SPDIP 28-Pin SOIC 28-Pin QFN Preliminary PIC18F4450 DC – 48 MHz 16384 8192 768 13 Ports Input Channels POR, BOR, RESET Instruction, ...
Page 12
... Timer1 Timer2 10-Bit EUSART Preliminary PORTA RA0/AN0 RA1/AN1 RA2/AN2/V - REF RA3/AN3/V + REF RA4/T0CKI/RCV RA5/AN4/HLVDIN OSC2/CLKO/RA6 PORTB RB0/AN12/INT0 RB1/AN10/INT1 RB2/AN8/INT2/VMO RB3/AN9/VPO RB4/AN11/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD PORTC RC0/T1OSO/T1CKI 8 RC1/T1OSI/UOE RC2/CCP1 RC4/D-/VM RC5/D+/VP RC6/TX/CK RC7/RX/DT PORTE (1) MCLR/V /RE3 PP USB © 2007 Microchip Technology Inc. ...
Page 13
... FIGURE 1-2: PIC18F4450 (40/44-PIN) BLOCK DIAGRAM Table Pointer<21> inc/dec logic PCLATU PCLATH 21 20 PCU PCH Program Counter 31 Level Stack Address Latch Program Memory STKPTR (24/32 Kbytes) Data Latch 8 Table Latch ROM Latch Instruction Bus <16> IR Instruction Decode & Control Internal Oscillator ...
Page 14
... Crystal Oscillator mode. O — In select modes, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output I = Input P = Power Preliminary Description © 2007 Microchip Technology Inc. ...
Page 15
... RA5 AN4 HLVDIN RA6 — — Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output © 2007 Microchip Technology Inc. PIC18F2450/4450 Pin Buffer Type Type PORTA is a bidirectional I/O port. I/O TTL Digital I/O. I Analog Analog input 0. ...
Page 16
... Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power Preliminary Description © 2007 Microchip Technology Inc. ...
Page 17
... USB Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output © 2007 Microchip Technology Inc. PIC18F2450/4450 Pin Buffer Type Type PORTC is a bidirectional I/O port. I/O ST Digital I/O. O — Timer1 oscillator output Timer1external clock input. I/O ST Digital I/O ...
Page 18
... PIC18F2450/4450 TABLE 1-3: PIC18F4450 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PDIP QFN TQFP MCLR/V /RE3 MCLR V PP RE3 OSC1/CLKI 13 32 OSC1 CLKI OSC2/CLKO/RA6 14 33 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output Note 1: These pins are No Connect unless the ICPRT Configuration bit is set ...
Page 19
... TABLE 1-3: PIC18F4450 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN TQFP RA0/AN0 2 19 RA0 AN0 RA1/AN1 3 20 RA1 AN1 RA2/AN2 REF RA2 AN2 V - REF RA3/AN3 REF RA3 AN3 V + REF RA4/T0CKI/RCV 6 23 RA4 T0CKI RCV RA5/AN4/HLVDIN 7 24 RA5 AN4 ...
Page 20
... PIC18F2450/4450 TABLE 1-3: PIC18F4450 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN TQFP RB0/AN12/INT0 33 9 RB0 AN12 INT0 RB1/AN10/INT1 34 10 RB1 AN10 INT1 RB2/AN8/INT2/VMO 35 11 RB2 AN8 INT2 VMO RB3/AN9/VPO 36 12 RB3 AN9 VPO RB4/AN11/KBI0 37 14 RB4 AN11 KBI0 ...
Page 21
... TABLE 1-3: PIC18F4450 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN TQFP RC0/T1OSO/T1CKI 15 34 RC0 T1OSO T1CKI RC1/T1OSI/UOE 16 35 RC1 T1OSI UOE RC2/CCP1 17 36 RC2 CCP1 RC4/D-/ RC4 D- VM RC5/D+/ RC5 D+ VP RC6/TX/ RC6 TX CK RC7/RX/ RC7 RX DT Legend: TTL = TTL compatible input ...
Page 22
... PIC18F2450/4450 TABLE 1-3: PIC18F4450 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN TQFP RD0 19 38 RD1 20 39 RD2 21 40 RD3 22 41 RD4 27 2 RD5 28 3 RD6 29 4 RD7 30 5 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels ...
Page 23
... TABLE 1-3: PIC18F4450 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN TQFP RE0/AN5 8 25 RE0 AN5 RE1/AN6 9 26 RE1 AN6 RE2/AN7 10 27 RE2 AN7 RE3 — — USB (1) NC/ICCK/ICPGC — — ICCK ICPGC (1) NC/ICDT/ICPGD — — ICDT ...
Page 24
... PIC18F2450/4450 NOTES: DS39760C-page 22 Preliminary © 2007 Microchip Technology Inc. ...
Page 25
... The OSCCON register (Register 2-1) selects the Active Clock mode primarily used in controlling clock switching in power-managed modes. Its use is discussed in Section 2.4.1 “Oscillator Control Register”. © 2007 Microchip Technology Inc. PIC18F2450/4450 2.2 Oscillator Types PIC18F2450/4450 devices can be operated in twelve distinct oscillator modes. In contrast with the non-USB PIC18 enhanced microcontrollers, four of these modes involve the use of two oscillator types at once ...
Page 26
... Internal RC Oscillator 31.25 kHz Preliminary USB Clock Source USBDIV 0 1 FSEN 1 USB Peripheral ÷ CPU 1 0 Primary Clock IDLEN Peripherals T1OSC Clock Control FOSC3:FOSC0 OSCCON<1:0> Clock Source Option for other Modules WDT, PWRT, FSCM and Two-Speed Start-up © 2007 Microchip Technology Inc. ...
Page 27
... DD See the notes following Table 2-2 for additional information. Resonators Used: 4.0 MHz 8.0 MHz 16.0 MHz © 2007 Microchip Technology Inc. PIC18F2450/4450 TABLE 2-2: Osc Type XT HS Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation ...
Page 28
... MHz which drives the PLL directly. FIGURE 2-6: PLL BLOCK DIAGRAM (HS MODE) HS/EC/ECIO/XT Oscillator Enable PLL Enable (from CONFIG1H Register) OSC2 Oscillator F IN and OSC1 F OUT Prescaler ÷24 Preliminary © 2007 Microchip Technology Inc. Phase Comparator Loop Filter VCO SYSCLK ...
Page 29
... OSC1/CLKI; the OSC2/ CLKO pin functions as a digital I/O (RA6). Of these four modes, only INTIO mode frees up an additional pin (OSC2/CLKO/RA6) for port I/O use. © 2007 Microchip Technology Inc. PIC18F2450/4450 2.3 Oscillator Settings for USB When the PIC18F2450/4450 is used for USB ...
Page 30
... MHz 40 MHz 20 MHz 13.33 MHz 10 MHz 48 MHz 32 MHz 24 MHz 16 MHz 24 MHz 12 MHz 8 MHz 6 MHz 48 MHz 32 MHz 24 MHz 16 MHz 20 MHz 10 MHz 6.67 MHz 5 MHz 48 MHz 32 MHz 24 MHz 16 MHz 16 MHz 8 MHz 5.33 MHz 4 MHz 48 MHz 32 MHz 24 MHz 16 MHz © 2007 Microchip Technology Inc. ...
Page 31
... Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24 MHz, USB clock of 6 MHz). Note 1: Only valid when the USBDIV Configuration bit is cleared. © 2007 Microchip Technology Inc. PIC18F2450/4450 Clock Mode MCU Clock Division (FOSC3:FOSC0) ...
Page 32
... The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Clock transitions are discussed in greater detail in Section 3.1.2 “Entering Power-Managed Modes”. Preliminary © 2007 Microchip Technology Inc. ...
Page 33
... Unimplemented: Read as ‘0’ bit 1-0 SCS1:SCS0: System Clock Select bits 1x = Internal oscillator 01 = Timer1 oscillator 00 = Primary oscillator Note 1: Depends on the state of the IESO Configuration bit. © 2007 Microchip Technology Inc. PIC18F2450/4450 (1) U-0 R U-0 — OSTS — Unimplemented bit, read as ‘0’ ...
Page 34
... OSC1 Pin At logic low (clock/4 output) Configured as PORTA, bit 6 Configured as PORTA, bit 6 At logic low (clock/4 output) Feedback inverter disabled at quiescent voltage level Preliminary (parameter 38, CSD OSC2 Pin © 2007 Microchip Technology Inc. ...
Page 35
... RC_IDLE 1 1x Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Clock is INTRC source. © 2007 Microchip Technology Inc. PIC18F2450/4450 3.1.1 CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three clock sources for power-managed modes. They are: power • The primary clock, as defined by the FOSC3:FOSC0 Configuration bits • ...
Page 36
... SEC_RUN mode will not occur. If the Timer1 oscillator is enabled but not yet running, device clocks will be delayed until the oscillator situations, initial oscillator operation is far from stable and unpredictable operation may result. Preliminary © 2007 Microchip Technology Inc. has started. In such ...
Page 37
... OST OSC PLL 2: Clock transition typically occurs within 2-4 T © 2007 Microchip Technology Inc. PIC18F2450/4450 Figure 3-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run ...
Page 38
... The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled n-1 n (1) Clock Transition OSC (1) (1) T PLL 1 2 n-1 n (2) Clock Transition OSTS bit Set = 2 ms (approx). These intervals are not shown to scale. . OSC Preliminary © 2007 Microchip Technology Inc. ...
Page 39
... (approx). These intervals are not shown to scale. OST OSC PLL © 2007 Microchip Technology Inc. PIC18F2450/4450 3.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to ‘ ...
Page 40
... SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled but not yet run- ning, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result CSD PC Preliminary © 2007 Microchip Technology Inc. ...
Page 41
... Section 8.0 “Interrupts”). © 2007 Microchip Technology Inc. PIC18F2450/4450 A fixed delay of interval, T event, is required when leaving Sleep and Idle modes. This delay is required for the CPU to prepare for execu- tion. Instruction execution resumes on the first clock cycle following this delay ...
Page 42
... INTRC None XT OST XTPLL, HSPLL T OST EC T CSD (1) INTRC T IOBST . PLL (parameter 39, Table 21-10), the INTRC stabilization period. IOBST Preliminary Clock Ready Status Bit (OSCCON) OSTS (3) ( OSTS (2) (4) (3) ( OSTS (2) (3) ( OSTS (2) (4) is the PLL lock time-out rc © 2007 Microchip Technology Inc. ...
Page 43
... Ripple Counter Note 1: This is the INTRC source from the internal oscillator and is separate from the RC oscillator of the CLKI pin. 2: See Table 4-2 for time-out situations. © 2007 Microchip Technology Inc. PIC18F2450/4450 A simplified block diagram of the on-chip Reset circuit is shown in Figure 4-1. ...
Page 44
... Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Rest). DS39760C-page 42 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary (2) R/W-0 R/W-0 POR BOR bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 45
... Reset occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any Power-on Reset. © 2007 Microchip Technology Inc. PIC18F2450/4450 FIGURE 4-2: V ...
Page 46
... BOR Operation BOR disabled; must be enabled by reprogramming the Configuration bits. BOR enabled in software; operation controlled by SBOREN. BOR enabled in hardware in Run and Idle modes, disabled during Sleep mode. BOR enabled in hardware; must be disabled by reprogramming the Configuration bits. Preliminary © 2007 Microchip Technology Inc. ...
Page 47
... Note (65.5 ms) is the nominal Power-up Timer (PWRT) delay the nominal time required for the PLL to lock. © 2007 Microchip Technology Inc. PIC18F2450/4450 4.5.3 PLL LOCK TIME-OUT With the PLL enabled in its PLL mode, the time-out sequence following a Power-on Reset is slightly differ- ent from other oscillator modes ...
Page 48
... PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS39760C-page 46 T PWRT T OST T PWRT T OST T PWRT T OST Preliminary © 2007 Microchip Technology Inc RISE < PWRT ): CASE CASE 2 DD ...
Page 49
... TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST ≈ max. First three stages of the Power-up Timer. T PLL © 2007 Microchip Technology Inc. PIC18F2450/4450 , V RISE > PWRT T OST T PWRT T ...
Page 50
... Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register Program Counter SBOREN 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h ( (1) ( Preliminary STKPTR Register POR BOR STKFUL STKUNF © 2007 Microchip Technology Inc. ...
Page 51
... See Table 4-3 for Reset value for specific condition. 5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2007 Microchip Technology Inc. PIC18F2450/4450 MCLR Resets, Power-on Reset, ...
Page 52
... Microchip Technology Inc. ...
Page 53
... See Table 4-3 for Reset value for specific condition. 5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2007 Microchip Technology Inc. PIC18F2450/4450 MCLR Resets, Power-on Reset, ...
Page 54
... Preliminary Wake-up via WDT or Interrupt ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu uu-u uuuu -uuu uuuu -uuu uuu- -uuu uuu- u--u uuuu u--u uuuu -uuu uuuu -uuu uuuu ---- -uuu uuuu uuuu © 2007 Microchip Technology Inc. ...
Page 55
... NOP instruction). The PIC18F2450 and PIC18F4450 each have 16 Kbytes of Flash memory and can store up to 8192 single-word instructions. PIC18 devices have two interrupt vectors. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h ...
Page 56
... The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. Return Address Stack<20:0> 11111 11110 11101 TOSL 34h 00011 001A34h 00010 Top-of-Stack 000D58h 00001 00000 Preliminary Stack Pointer STKPTR<4:0> 00010 © 2007 Microchip Technology Inc. ...
Page 57
... SP4:SP0: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software POR. © 2007 Microchip Technology Inc. PIC18F2450/4450 When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero ...
Page 58
... Data is transferred to or from program memory one byte at a time. Table read and table write operations are discussed further in Section 6.1 “Table Reads and Table Writes”. Preliminary © 2007 Microchip Technology Inc. ...
Page 59
... Note: All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2007 Microchip Technology Inc. PIC18F2450/4450 5.2.2 INSTRUCTION FLOW/PIPELINING An “ ...
Page 60
... REG1 ; is RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code Preliminary address embedded into the Word Address ↓ 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h © 2007 Microchip Technology Inc. ...
Page 61
... Additional information on USB RAM and buffer operation is provided in Section 14.0 “Universal Serial Bus (USB)”. © 2007 Microchip Technology Inc. PIC18F2450/4450 5.3.2 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible ...
Page 62
... RAM (from Bank 0). The remaining 160 bytes are Special Function Registers (from Bank 15). When The BSR specifies the bank used by the instruction. Access Bank 00h Access RAM Low 5Fh 60h Access RAM High (SFRs) FFh © 2007 Microchip Technology Inc. ...
Page 63
... Access RAM bit (the ‘a’ parameter in the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, © 2007 Microchip Technology Inc. PIC18F2450/4450 Data Memory 000h ...
Page 64
... UEIE LATB F6Ah UEIR LATA F69h UIE (2) — F68h UIR (2) — F67h UFRMH (2) — F66h UFRML (2) (2) — F65h — (2) PORTE F64h — (3) (2) PORTD F63h — (2) PORTC F62h — (2) PORTB F61h — (2) PORTA F60h — © 2007 Microchip Technology Inc. ...
Page 65
... RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’. 6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0). © 2007 Microchip Technology Inc. PIC18F2450/4450 Bit 4 Bit 3 Bit 2 — ...
Page 66
... TRISB0 1111 1111 51, 103 TRISA0 51, 100 -111 1111 LATE0 51, 110 ---- -xxx LATD0 51, 108 xxxx xxxx LATC0 51, 106 xx-- -xxx LATB0 xxxx xxxx 51, 103 LATA0 51, 100 -xxx xxxx (3) (3) RE0 51, 109 ---- x000 RD0 51, 108 xxxx xxxx © 2007 Microchip Technology Inc. ...
Page 67
... RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’. 6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0). © 2007 Microchip Technology Inc. PIC18F2450/4450 Bit 4 Bit 3 Bit 2 ...
Page 68
... Table 19-2 and Table 19-3. Note: The C and DC bits operate as the Borrow and Digit Borrow bits, respectively, in subtraction. R/W-x R/W-x R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-x R/W-x (1) ( bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 69
... Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (Section 5.3.4 “General © 2007 Microchip Technology Inc. PIC18F2450/4450 Purpose Register File” location in the Access Bank (Section 5.3.3 “Access Bank”) as the data source for the instruction. The Access RAM bit ‘ ...
Page 70
... BSR and the Access RAM bit have no effect on determining the target address. ADDWF, INDF1, 1 FSR1H:FSR1L Preliminary 000h Bank 0 100h Bank 1 200h Bank 2 300h 0 Bank 3 through Bank 13 E00h Bank 14 Bank 14 F00h Bank 15 FFFh Data Memory © 2007 Microchip Technology Inc. ...
Page 71
... In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. © 2007 Microchip Technology Inc. PIC18F2450/4450 5.4.3.3 Operations by FSRs on FSRs Indirect Addressing operations that target other FSRs or virtual registers represent special cases ...
Page 72
... Figure 5-8. Those who desire to use byte-oriented or bit-oriented instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. This is described in more detail in Section 19.2.1 “Extended Instruction Syntax”. Preliminary © 2007 Microchip Technology Inc. ...
Page 73
... The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. © 2007 Microchip Technology Inc. PIC18F2450/4450 000h 060h 080h Bank 0 100h Bank 1 ...
Page 74
... BSR remains unchanged. Direct Addressing, using the BSR to select the data memory bank, operates in the same manner as previously described. Bank 0 Window Bank 1 Bank 2 through Bank 14 Bank 15 SFRs Data Memory Preliminary 00h Bank 1 “Window” 5Fh 60h SFRs FFh Access Bank © 2007 Microchip Technology Inc. ...
Page 75
... TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2007 Microchip Technology Inc. PIC18F2450/4450 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
Page 76
... Reset or a write operation was Reading attempted improperly. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. Preliminary Table Latch (8-bit) TABLAT © 2007 Microchip Technology Inc. ...
Page 77
... The WR bit can only be set (not cleared) in software Write cycle complete bit 0 Unimplemented: Read as ‘0’ Note 1: When a WRERR occurs, the CFGS bit is not cleared. This allows tracing of the error condition. © 2007 Microchip Technology Inc. PIC18F2450/4450 R/W-0 R/W-x R/W-0 (1) FREE ...
Page 78
... Figure 6-3 describes the relevant boundaries of the TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 TABLE READ – TBLPTR<21:0> Preliminary TBLPTRL 0 © 2007 Microchip Technology Inc. ...
Page 79
... WORD_EVEN TBLRD*+ MOVF TABLAT, W MOVF WORD_ODD © 2007 Microchip Technology Inc. PIC18F2450/4450 TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
Page 80
... Re-enable interrupts. ; load TBLPTR with the base ; address of the memory block ; access Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts Preliminary © 2007 Microchip Technology Inc. ...
Page 81
... WREN to enable byte writes. 8. Disable interrupts. 9. Write 55h to EECON2. © 2007 Microchip Technology Inc. PIC18F2450/4450 The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. ...
Page 82
... TBLWT holding register. ; loop until buffers are full Preliminary © 2007 Microchip Technology Inc. ...
Page 83
... USBIF PIE2 OSCFIE — USBIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash access. © 2007 Microchip Technology Inc. PIC18F2450/4450 ; access Flash program memory ; enable write to memory ; disable interrupts ; write 55h ; write 0AAh ; start program (CPU stall) ...
Page 84
... PIC18F2450/4450 NOTES: DS39760C-page 82 Preliminary © 2007 Microchip Technology Inc. ...
Page 85
... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2007 Microchip Technology Inc. PIC18F2450/4450 EXAMPLE 7- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL ...
Page 86
... PRODL RES1 Add cross PRODH products ; WREG ; ; ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products ; WREG ; ; ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H © 2007 Microchip Technology Inc. ...
Page 87
... INTCON<7> is the GIE bit which enables/disables all interrupt sources. All interrupts branch to address 000008h in Compatibility mode. © 2007 Microchip Technology Inc. PIC18F2450/4450 When an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. If the IPEN bit is cleared, this is the GIE bit ...
Page 88
... INT2IF INT2IE INT2IP IPEN IPEN PEIE/GIEL IPEN TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Preliminary © 2007 Microchip Technology Inc. Wake- Sleep Mode Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h PEIE/GIEL GIE/GIEH ...
Page 89
... None of the RB7:RB4 pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2007 Microchip Technology Inc. PIC18F2450/4450 Note: Interrupt flag bits are set when an interrupt ...
Page 90
... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39760C-page 88 R/W-1 U-0 R/W-1 — INTEDG2 TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 R/W-1 — RBIP bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 91
... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2007 Microchip Technology Inc. PIC18F2450/4450 R/W-0 ...
Page 92
... R-0 U-0 R/W-0 TXIF — CCP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. should ensure the R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown ...
Page 93
... Unimplemented: Read as ‘0’ bit 2 HLVDIF: High/Low-Voltage Detect Interrupt Flag bit high/low-voltage condition occurred high/low-voltage event has occurred bit 1-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC18F2450/4450 U-0 U-0 R/W-0 — — HLVDIF U = Unimplemented bit, read as ‘0’ ...
Page 94
... TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt DS39760C-page 92 R/W-0 U-0 R/W-0 TXIE — CCP1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 95
... Disabled bit 4-3 Unimplemented: Read as ‘0’ bit 2 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC18F2450/4450 U-0 U-0 R/W-0 — — HLVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 96
... Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority DS39760C-page 94 R/W-1 U-0 R/W-1 TXIP — CCP1IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 97
... Low priority bit 4-3 Unimplemented: Read as ‘0’ bit 2 HLVDIP: High/Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC18F2450/4450 U-0 U-0 R/W-1 — — HLVDIP U = Unimplemented bit, read as ‘0’ ...
Page 98
... The actual Reset value of POR is determined by the type of device Reset. See Register 4-1 for additional information. DS39760C-page 96 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary (2) R/W-0 R/W-0 POR BOR bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 99
... MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS © 2007 Microchip Technology Inc. PIC18F2450/4450 8.8 TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L register pair (FFFFh → 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON< ...
Page 100
... PIC18F2450/4450 NOTES: DS39760C-page 98 Preliminary © 2007 Microchip Technology Inc. ...
Page 101
... Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). © 2007 Microchip Technology Inc. PIC18F2450/4450 Reading the PORTA register reads the status of the pins; writing to it will write to the port latch. ...
Page 102
... LATA3 LATA2 TRISA5 TRISA4 TRISA3 TRISA2 VCFG1 VCFG0 PCFG3 PCFG2 SE0 PKTDIS USBEN RESUME SUSPND Preliminary Description /4); available in EC, ECPLL and OSC Reset Bit 1 Bit 0 Values on Page: RA1 RA0 51 LATA1 LATA0 51 TRISA1 TRISA0 51 PCFG1 PCFG0 50 — 52 © 2007 Microchip Technology Inc. ...
Page 103
... MOVFF (ANY), PORTB instruction). This will end the mismatch condition. b) Clear flag bit, RBIF. © 2007 Microchip Technology Inc. PIC18F2450/4450 A mismatch condition will continue to set flag bit, RBIF. Reading PORTB will end the mismatch condition and allow flag bit, RBIF cleared. ...
Page 104
... PORTB<7> data input; weak pull-up when RBPU bit is cleared. IN TTL Interrupt-on-pin change. DIG Serial execution data output for ICSP and ICD operation Serial execution data input for ICSP and ICD operation. Preliminary Description (1) (1) (1) (1) (1) (2) (2) (2) © 2007 Microchip Technology Inc. ...
Page 105
... RBPU INTEDG0 INTEDG1 INTEDG2 INTCON3 INT2IP INT1IP ADCON1 — — UCON — PPBRST Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB. © 2007 Microchip Technology Inc. PIC18F2450/4450 Bit 5 Bit 4 Bit 3 Bit 2 RB5 RB4 RB3 RB2 LATB5 LATB4 ...
Page 106
... EXAMPLE 9-3: CLRF PORTC CLRF LATC MOVLW 07h MOVWF TRISC Preliminary transceiver must be disabled INITIALIZING PORTC ; Initialize PORTC by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Value used to ; initialize data ; direction ; RC<5:0> as outputs ; RC<7:6> as inputs © 2007 Microchip Technology Inc. ...
Page 107
... TTL = TTL Buffer Input, XCVR = USB Transceiver Don’t care (TRIS bit does not affect port direction or is overridden for this option) Note 1: RC4 and RC5 do not have corresponding TRISC bits. In Port mode, these pins are input only. USB data direction is determined by the USB configuration. © 2007 Microchip Technology Inc. PIC18F2450/4450 I/O I/O Type OUT DIG LATC< ...
Page 108
... DS39760C-page 106 Bit 5 Bit 4 Bit 3 Bit 2 (1) (1) RC5 RC4 — RC2 — — — LATC2 — — — TRISC2 SE0 PKTDIS USBEN RESUME SUSPND Preliminary Reset Bit 1 Bit 0 Values on Page: RC1 RC0 51 LATC1 LATC0 51 TRISC1 TRISC0 51 — 52 © 2007 Microchip Technology Inc. ...
Page 109
... PORTD. All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Note Power-on Reset, these pins are configured as digital inputs. © 2007 Microchip Technology Inc. PIC18F2450/4450 EXAMPLE 9-4: INITIALIZING PORTD CLRF PORTD ; Initialize PORTD by ...
Page 110
... DIG LATD<7> data output PORTD<7> data input. Bit 5 Bit 4 Bit 3 Bit 2 RD5 RD4 RD3 RD2 LATD5 LATD4 LATD3 LATD2 TRISD5 TRISD4 TRISD3 TRISD2 Preliminary Description Reset Bit 1 Bit 0 Values on Page: RD1 RD0 51 LATD1 LATD0 51 TRISD1 TRISD0 51 © 2007 Microchip Technology Inc. ...
Page 111
... RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are implemented only when PORTE is implemented (i.e., 40/44-pin devices). 3: Unimplemented in 28-pin devices; read as ‘0’. © 2007 Microchip Technology Inc. PIC18F2450/4450 functions as a digital input only pin; as such, it does not have TRIS or LAT bits associated with its operation. ...
Page 112
... Bit 4 Bit 3 Bit 2 (1,2) — — RE3 RE2 — — — LATE2 — — — TRISE2 VCFG1 VCFG0 PCFG3 PCFG2 Preliminary Description Reset Bit 1 Bit 0 Values on Page: (3) (3) (3) RE1 RE0 51 LATE1 LATE0 51 TRISE1 TRISE0 51 PCFG1 PCFG0 50 © 2007 Microchip Technology Inc. ...
Page 113
... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value © 2007 Microchip Technology Inc. PIC18F2450/4450 The T0CON register (Register 10-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 10-1 ...
Page 114
... Sync with Internal TMR0L Clocks Delay Preliminary ). There is a delay between OSC Set TMR0IF TMR0L on Overflow 8 8 Internal Data Bus Set TMR0 TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus © 2007 Microchip Technology Inc. ...
Page 115
... Legend: — = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0. Note 1: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’. © 2007 Microchip Technology Inc. PIC18F2450/4450 10.3.1 SWITCHING PRESCALER ...
Page 116
... PIC18F2450/4450 NOTES: DS39760C-page 114 Preliminary © 2007 Microchip Technology Inc. ...
Page 117
... OSC bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2007 Microchip Technology Inc. PIC18F2450/4450 A simplified block diagram of the Timer1 module is shown in Figure 11-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 11-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
Page 118
... Special Event Trigger) 8 Preliminary 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR1H 8 8 Internal Data Bus © 2007 Microchip Technology Inc. ...
Page 119
... T1OSI XTAL 32.768 kHz T1OSO Note: See the Notes with Table 11-1 for additional information about capacitor selection. © 2007 Microchip Technology Inc. PIC18F2450/4450 TABLE 11-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Osc Type Freq LP 32 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
Page 120
... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. Preliminary a Special Event Trigger © 2007 Microchip Technology Inc. ...
Page 121
... CPFSGT hours RETURN CLRF hours RETURN © 2007 Microchip Technology Inc. PIC18F2450/4450 following a later Timer1 increment. This can be done by monitoring TMR1L within the interrupt routine until it increments, and then updating the TMR1H:TMR1L register pair while the clock is low, or one-half of the period of the clock source. Assuming that Timer1 is being used as a Real-Time Clock, the clock source ...
Page 122
... DS39760C-page 120 Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF RCIF TXIF — CCP1IF RCIE TXIE — CCP1IE RCIP TXIP — CCP1IP Preliminary Reset Bit 1 Bit 0 Values on Page: INT0IF RBIF 49 TMR2IF TMR1IF 51 TMR2IE TMR1IE 51 TMR2IP TMR1IP TMR1CS TMR1ON 50 © 2007 Microchip Technology Inc. ...
Page 123
... TMR2ON: Timer2 On bit 1 = Timer2 Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2007 Microchip Technology Inc. PIC18F2450/4450 12.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 2-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by- 16 prescale options. These are selected by the prescaler control bits, T2CKPS1:T2CKPS0 (T2CON< ...
Page 124
... Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TXIF — CCP1IF TMR2IF TXIE — CCP1IE TMR2IE TXIP — CCP1IP TMR2IP Preliminary Set TMR2IF TMR2 Output (to PWM) PR2 8 Reset Bit 1 Bit 0 Values on Page: INT0IF RBIF 49 TMR1IF 51 TMR1IE 51 TMR1IP © 2007 Microchip Technology Inc. ...
Page 125
... Compare mode: generate software interrupt on compare match (CCP1IF bit is set, CCP1 pin reflects I/O state) 1011 = Compare mode: trigger special event, reset timer and start A/D conversion on CCP1 match (CCP1IF bit is set) 11xx = PWM mode © 2007 Microchip Technology Inc. PIC18F2450/4450 R/W-0 R/W-0 R/W-0 ...
Page 126
... Edge Detect 4 4 Preliminary CHANGING BETWEEN CAPTURE PRESCALERS (CCP1 SHOWN) ; Turn CCP module off ; Load WREG with the ; new prescaler mode ; value and CCP ON ; Load CCP1CON with ; this value CCPR1H CCPR1L TMR1 Enable TMR1H TMR1L © 2007 Microchip Technology Inc. ...
Page 127
... COMPARE MODE OPERATION BLOCK DIAGRAM CCPR1H CCPR1L Compare Comparator TMR1H TMR1L © 2007 Microchip Technology Inc. PIC18F2450/4450 13.3.3 SOFTWARE INTERRUPT MODE When the Generate Software Interrupt mode is chosen (CCP1M3:CCP1M0 = 1010), the CCP1 pin is not affected. Only a CCP interrupt is generated, if enabled, and the CCP1IE bit is set. ...
Page 128
... CCP1IP — — — TRISC2 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 Preliminary Reset Bit 1 Bit 0 Values on Page: INT0IF RBIF 49 PD POR BOR 50 TMR2IF TMR1IF 51 TMR2IE TMR1IE 51 TMR2IP TMR1IP 51 TRISC1 TRISC0 TMR1CS TMR1ON © 2007 Microchip Technology Inc. ...
Page 129
... FIGURE 13-4: PWM OUTPUT Period Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2 © 2007 Microchip Technology Inc. PIC18F2450/4450 13.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula: EQUATION 13-1: PWM Period = [(PR2 • ...
Page 130
... DC1B0 CCP1M3 CCP1M2 Preliminary 156.25 kHz 312.50 kHz 416.67 kHz 3Fh 1Fh 17h 8 7 6.58 Reset Bit 2 Bit 1 Bit 0 Values on Page: INT0IF RBIF 49 PD POR BOR 50 TMR2IF TMR1IF 51 TMR2IE TMR1IE 51 TMR2IP TMR1IP 51 TRISC1 TRISC0 CCP1M1 CCP1M0 50 © 2007 Microchip Technology Inc. ...
Page 131
... Note 1: This signal is only available if the internal transceiver is disabled (UTRDIS = 1). 2: The pull-ups can be supplied either from the not enable the internal regulator when using an external 3.3V supply. © 2007 Microchip Technology Inc. PIC18F2450/4450 any USB host and the PIC be interfaced directly to the USB, utilizing the internal transceiver can be connected through an external transceiver ...
Page 132
... R/C-0 R/W-0 R/W-0 PKTDIS USBEN RESUME U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 U-0 SUSPND — bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 133
... These include: • Bus Speed (full speed versus low speed) • On-Chip Transceiver Enable • Ping-Pong Buffer Usage © 2007 Microchip Technology Inc. PIC18F2450/4450 The UCFG register also contains two bits which aid in module testing, debugging and USB certifications. These bits control output enable state monitoring and eye pattern generation ...
Page 134
... SIE that can’t be captured with the RCV signal. The combinations of states of these signals and their interpretation are listed in Table 14-1 and Table 14-2. Preliminary R/W-0 R/W-0 PPB1 PPB0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 135
... Ping-Pong Buffer Configuration The usage of ping-pong buffers is configured using the PPB1:PPB0 bits. Refer to Section 14.4.4 “Ping-Pong Buffering” for a complete explanation of the ping-pong buffers. © 2007 Microchip Technology Inc. PIC18F2450/4450 14.2.2.6 USB Output Enable Monitor The USB OE monitor provides indication as to whether the SIE is listening to the bus or actively driving the bus ...
Page 136
... FIFO for USTAT Data Bus R-x R-x R-x ENDP1 ENDP0 DIR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary is full, the SIE will Clearing TRNIF Advances FIFO R-x U-0 (1) PPBI — bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 137
... EPSTALL: Endpoint Stall Enable bit 1 = Endpoint n is stalled 0 = Endpoint n is not stalled Note 1: Valid only if Endpoint n is enabled; otherwise, the bit is ignored. © 2007 Microchip Technology Inc. PIC18F2450/4450 transactions. For Endpoint 0, this bit should always be cleared since the Endpoint 0 as the default control endpoint. ...
Page 138
... Bank15 Preliminary IMPLEMENTATION OF USB RAM IN DATA MEMORY SPACE 000h User Data 1FFh 200h Unused Unused 3FFh 400h Buffer Descriptors, USB Data or User Data 4FFh 500h USB Data or User Data 7FFh 800h Unused F00h F80h SFRs FFFh © 2007 Microchip Technology Inc. ...
Page 139
... UEPn register. All BD registers are available in USB RAM. The BD for each endpoint should be set up prior to enabling the endpoint. © 2007 Microchip Technology Inc. PIC18F2450/4450 14.4.1 BD STATUS AND CONFIGURATION Buffer descriptors not only define the size of an endpoint buffer, but also determine its configuration and control ...
Page 140
... Device Response after Receiving Packet DTS Handshake UOWN TRNIF ACK ACK ACK ACK ACK NAK Preliminary “BD Byte Count” for more BDnSTAT and USTAT Status Updated Not Updated Updated Not Updated Updated Not Updated © 2007 Microchip Technology Inc. ...
Page 141
... This bit must be initialized by the user to the desired value prior to enabling the USB module. 2: This bit is ignored unless DTSEN = these bits are set, USB communication may not work. Hence, these bits should always be maintained as ‘0’. © 2007 Microchip Technology Inc. PIC18F2450/4450 R/W-x R/W-x (3) — ...
Page 142
... R/W-x R/W-x R/W-x PID2 PID1 PID0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary When developing USB R/W-x R/W-x BC9 BC8 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 143
... Maximum Memory Used: 128 bytes Maximum BDs: 32 (BD0 to BD31) Note: Memory area not shown to scale. © 2007 Microchip Technology Inc. PIC18F2450/4450 by the SIE), the pointer is toggled to the ODD BD. After the completion of the next transaction, the pointer is toggled back to the EVEN BD and so on. ...
Page 144
... Bit 2 Bit 1 Bit 0 (2) PID0 BC9 BC8 (3) BSTALL © 2007 Microchip Technology Inc. ...
Page 145
... The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers will spread across multiple frames. © 2007 Microchip Technology Inc. PIC18F2450/4450 Figure 14-8 shows the interrupt logic for the USB module. There are two layers of interrupt registers in the USB module. The top level consists of overall USB status interrupts ...
Page 146
... The flag bits can also be set in software which can aid in firmware debugging. R/W-0 R/W-0 R/W-0 (1) (2) (3) IDLEIF TRNIF ACTVIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (3) (4) Preliminary R-0 R/W-0 (4) UERRIF URSTIF bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 147
... SUSPND bit, the USB module may not be immediately operational while waiting for the 96 MHz PLL to lock. The application code should clear the ACTVIF bit as shown in Example 14-1. © 2007 Microchip Technology Inc. PIC18F2450/4450 EXAMPLE 14-1: CLEARING ACTVIF BIT (UIR<2>) ...
Page 148
... The flag bits are still set by their interrupt conditions, allowing them to be polled and serviced without actually generating an interrupt. R/W-0 R/W-0 R/W-0 IDLEIE TRNIE ACTVIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 UERRIE URSTIE bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 149
... PIDEF: PID Check Failure Flag bit 1 = PID check failed 0 = PID check passed © 2007 Microchip Technology Inc. PIC18F2450/4450 Each error bit is set as soon as the error condition is detected. Thus, the interrupt will typically not correspond with the end of a token being processed. ...
Page 150
... R/W-0 R/W-0 R/W-0 BTOEE DFN8EE CRC16EE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary interrupt condition to the R/W-0 R/W-0 CRC5EE PIDEE bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 151
... BUS ~5V 100 kΩ V SELF ~5V 100 kΩ © 2007 Microchip Technology Inc. PIC18F2450/4450 14.6.3 DUAL POWER WITH SELF-POWER DOMINANCE Some applications may require a dual power option. This allows the application to use internal power prima- rily, but switch to power from the USB when no internal power is available ...
Page 152
... CRC5EF PIDEF 52 CRC5EE PIDEE 52 EPINEN EPSTALL 52 EPINEN EPSTALL 52 EPINEN EPSTALL 52 EPINEN EPSTALL 52 EPINEN EPSTALL 52 EPINEN EPSTALL 52 EPINEN EPSTALL 52 EPINEN EPSTALL 52 EPINEN EPSTALL 52 EPINEN EPSTALL 51 EPINEN EPSTALL 51 EPINEN EPSTALL 51 EPINEN EPSTALL 51 EPINEN EPSTALL 51 EPINEN EPSTALL 51 EPINEN EPSTALL 51 © 2007 Microchip Technology Inc. ...
Page 153
... Figure 14-9 shows an example of a transaction within a frame. FIGURE 14-13: USB LAYERS Interface Endpoint Endpoint © 2007 Microchip Technology Inc. PIC18F2450/4450 14.9.3 TRANSFERS There are four transfer types defined in the USB specification. • Isochronous: This type provides a transfer method for large amounts of data (up to 1023 bytes) with timely delivery ensured ...
Page 154
... USB device. In custom applications, a driver may need to be developed. Fortunately, drivers are available for most common host systems for the most common classes of devices. Thus, these drivers can be reused. Preliminary © 2007 Microchip Technology Inc. about the layer Framework”) they optionally support ...
Page 155
... Break character transmission • Synchronous – Master (half-duplex) with selectable clock polarity • Synchronous – Slave (half-duplex) with selectable clock polarity © 2007 Microchip Technology Inc. PIC18F2450/4450 The pins of the Enhanced USART are multiplexed with PORTC. In order to configure RC6/TX/CK and RC7/RX EUSART: • ...
Page 156
... SREN/CREN overrides TXEN in Sync mode with the exception that SREN has no effect in Synchronous Slave mode. DS39760C-page 154 R/W-0 R/W-0 R/W-0 (1) SYNC SENDB BRGH U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R-1 R/W-0 TRMT TX9D bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 157
... OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN overrun error bit 0 RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. © 2007 Microchip Technology Inc. PIC18F2450/4450 R/W-0 R/W-0 R-0 CREN ...
Page 158
... Baud rate measurement disabled or completed Synchronous mode: Unused in this mode. DS39760C-page 156 R/W-0 R/W-0 U-0 SCKP BRG16 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 WUE ABDEN bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 159
... Legend Don’t care value of SPBRGH:SPBRG register pair © 2007 Microchip Technology Inc. PIC18F2450/4450 the high baud rate (BRGH = 1) or the 16-bit BRG to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. Writing a new value to the SPBRGH:SPBRG registers causes the BRG timer to be reset (or cleared) ...
Page 160
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. DS39760C-page 158 Bit 5 Bit 4 Bit 3 Bit 2 TXEN SYNC SENDB BRGH SREN CREN ADDEN FERR — SCKP BRG16 — Preliminary Reset Bit 1 Bit 0 Values on Page: TRMT TX9D 51 OERR RX9D 51 WUE ABDEN © 2007 Microchip Technology Inc. ...
Page 161
... Microchip Technology Inc. PIC18F2450/4450 SYNC = 0, BRGH = 0, BRG16 = 20.000 MHz F = 10.000 MHz OSC OSC SPBRG Actual % Rate value Rate Error Error (K) (decimal) (K) — ...
Page 162
... Error (K) (decimal) (decimal) 8332 0.300 -0.01 6665 2082 1.200 -0.04 1665 1040 2.400 -0.04 832 259 9.615 -0.16 207 129 19.230 -0.16 103 42 57.142 0. 117.647 -2.12 16 SPBRG value (decimal) 832 207 103 25 12 — — © 2007 Microchip Technology Inc. ...
Page 163
... SPBRGH register. Refer to Table 15-4 for counter clock rates to the BRG. © 2007 Microchip Technology Inc. PIC18F2450/4450 While the ABD sequence takes place, the EUSART state machine is held in Idle. The RCIF interrupt is set once the fifth rising edge detected ...
Page 164
... RX pin ABDOVF bit BRG Value XXXXh DS39760C-page 162 Edge #1 Edge #2 Edge #3 bit 3 Start bit 1 bit 0 bit 2 bit 4 XXXXh XXXXh Start bit 0 0000h Preliminary 001Ch Edge #4 Edge #5 bit 7 bit 5 Stop bit bit 6 Auto-Cleared 1Ch 00h FFFFh 0000h © 2007 Microchip Technology Inc. ...
Page 165
... TXEN BRG16 SPBRGH SPBRG Baud Rate Generator © 2007 Microchip Technology Inc. PIC18F2450/4450 Once the TXREG register transfers the data to the TSR register (occurs in one T empty and the TXIF flag bit (PIR1<4>) is set. This inter- rupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXIE (PIE1< ...
Page 166
... Stop bit Start bit bit 7/8 bit 0 Stop bit Word 2 Word 2 Transmit Shift Reg. Reset Bit 1 Bit 0 Values on Page: INT0IF RBIF 49 TMR2IF TMR1IF 51 TMR2IE TMR1IE 51 TMR2IP TMR1IP 51 OERR RX9D 51 50 TRMT TX9D 51 WUE ABDEN © 2007 Microchip Technology Inc. ...
Page 167
... Baud Rate CLK BRG16 SPBRGH SPBRG Baud Rate Generator Pin Buffer and Control RX SPEN © 2007 Microchip Technology Inc. PIC18F2450/4450 15.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. ...
Page 168
... SYNC SENDB BRGH — SCKP BRG16 — Preliminary Start bit Stop Stop bit 7/8 bit bit Reset Bit 1 Bit 0 Values on Page: INT0IF RBIF 49 TMR2IF TMR1IF 51 TMR2IE TMR1IE 51 TMR2IP TMR1IP 51 OERR RX9D 51 50 TRMT TX9D 51 WUE ABDEN © 2007 Microchip Technology Inc. ...
Page 169
... If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. 2: The EUSART remains in Idle while the WUE bit is set. © 2007 Microchip Technology Inc. PIC18F2450/4450 (EOC) and cause data or framing errors. To work prop- erly, therefore, the initial character in the transmission must be all ‘ ...
Page 170
... Note that following a Break character, the user will typically want to enable the Auto-Baud Rate Detect feature. For both methods, the user can set the ABD bit once the TXIF interrupt is observed. bit 0 bit 1 bit 11 Break Auto-Cleared Preliminary © 2007 Microchip Technology Inc. Stop bit ...
Page 171
... TRMT bit ‘1’ TXEN bit Note: Sync Master mode (SPBRG = 0), continuous transmission of two 8-bit words. © 2007 Microchip Technology Inc. PIC18F2450/4450 Once the TXREG register transfers the data to the TSR register (occurs in one T empty and the TXIF flag bit (PIR1<4>) is set. The interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXIE (PIE1< ...
Page 172
... CCP1IP SREN CREN ADDEN FERR TXEN SYNC SENDB BRGH — SCKP BRG16 — Preliminary bit 6 bit 7 Reset Bit 1 Bit 0 Values on Page: INT0IF RBIF 49 TMR2IF TMR1IF 51 TMR2IE TMR1IE 51 TMR2IP TMR1IP 51 OERR RX9D 51 50 TRMT TX9D 51 WUE ABDEN © 2007 Microchip Technology Inc. ...
Page 173
... EUSART Baud Rate Generator Register High Byte SPBRG EUSART Baud Rate Generator Register Low Byte Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception. © 2007 Microchip Technology Inc. PIC18F2450/4450 3. Ensure bits, CREN and SREN, are clear. ...
Page 174
... TXIP — CCP1IP SREN CREN ADDEN FERR TXEN SYNC SENDB BRGH — SCKP BRG16 — Preliminary Reset Bit 1 Bit 0 Values on Page: INT0IF RBIF 49 TMR2IF TMR1IF 51 TMR2IE TMR1IE 51 TMR2IP TMR1IP 51 OERR RX9D 51 50 TRMT TX9D 51 WUE ABDEN © 2007 Microchip Technology Inc. ...
Page 175
... EUSART Baud Rate Generator Register High Byte SPBRG EUSART Baud Rate Generator Register Low Byte Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception. © 2007 Microchip Technology Inc. PIC18F2450/4450 To set up a Synchronous Slave Reception: 1. ...
Page 176
... PIC18F2450/4450 NOTES: DS39760C-page 174 Preliminary © 2007 Microchip Technology Inc. ...
Page 177
... Note 1: These channels are not implemented on 28-pin devices. 2: Performing a conversion on unimplemented channels will return a floating input measurement. © 2007 Microchip Technology Inc. PIC18F2450/4450 The ADCON0 register, shown in Register 16-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 16-2, configures the functions of the port pins ...
Page 178
... AN5 through AN7 are available only on 40/44-pin devices. DS39760C-page 176 (1) R/W-0 R/W-0 R/W VCFG0 PCFG3 PCFG2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared - source) REF + source) REF Digital I/O Preliminary (1) (1) (1) R/W R/W PCFG1 PCFG0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 179
... F /2 OSC Note 1: If the A/D F clock source is selected, a delay of one T RC clock starts. This allows the SLEEP instruction to be executed before starting a conversion. © 2007 Microchip Technology Inc. PIC18F2450/4450 R/W-0 R/W-0 R/W-0 ACQT1 ACQT0 ADCS2 U = Unimplemented bit, read as ‘0’ ...
Page 180
... CHS3:CHS0 V AIN (Input Voltage) VCFG1:VCFG0 ( REF REF and Preliminary 1100 AN12 1011 AN11 1010 AN10 1001 AN9 1000 AN8 0111 (1) AN7 0110 (1) AN6 0101 (1) AN5 0100 AN4 0011 AN3 0010 AN2 0001 AN1 0000 AN0 © 2007 Microchip Technology Inc. ...
Page 181
... SS = Sampling Switch C = Sample/hold Capacitance (from DAC) HOLD R = Sampling Switch Resistance SS © 2007 Microchip Technology Inc. PIC18F2450/4450 5. Wait for A/D conversion to complete, by either: • Polling for the GO/DONE bit to be cleared OR • Waiting for the A/D interrupt 6. Read A/D Result registers (ADRESH:ADRESL); ...
Page 182
... The sampling assumptions: C HOLD Rs Conversion Error V DD Temperature (- HOLD ln(1/2048) S COFF ) ln(1/2047) μs Preliminary the minimum acquisition time, . This calculation is ACQ the following application system = 2.5 kΩ ≤ 1/2 LSb 5V → kΩ 85°C (system max ms. © 2007 Microchip Technology Inc. ...
Page 183
... For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D accuracy may be out of specification. 4: Low-power devices only. © 2007 Microchip Technology Inc. PIC18F2450/4450 16.3 Selecting the A/D Conversion Clock The A/D conversion time per bit is defined as T ...
Page 184
... RC 3: The PBADEN Register 3H configures PORTB pins to reset as analog or digital pins by control- ling how the PCFG0 bits in ADCON1 are reset. Preliminary © 2007 Microchip Technology Inc. input will be accurately bit in Configuration ...
Page 185
... Conversion starts Time (Holding capacitor is disconnected) Set GO/DONE bit (Holding capacitor continues acquiring input) © 2007 Microchip Technology Inc. PIC18F2450/4450 After the A/D conversion is completed or aborted wait is required before the next acquisition can be AD started. After this wait, acquisition on the selected channel is automatically started ...
Page 186
... TMR2IP TMR1IP 51 — — 51 — — 51 — — GO/DONE ADON 50 PCFG1 PCFG0 50 ADCS1 ADCS0 50 RA1 RA0 51 TRISA1 TRISA0 51 RB1 RB0 51 TRISB1 TRISB0 51 LATB1 LATB0 51 (4) (4) (4) RE1 RE0 51 (4) (4) (4) TRISE1 TRISE0 51 (4) (4) (4) LATE1 LATE0 51 © 2007 Microchip Technology Inc. ...
Page 187
... Minimum setting Note 1: See Table 21-4 in Section 21.0 “Electrical Characteristics” for specifications. © 2007 Microchip Technology Inc. PIC18F2450/4450 The High/Low-Voltage (Register 17-1) completely controls the operation of the HLVD module. This allows the circuitry to be “turned off” by the user under software control which minimizes the current consumption for the device ...
Page 188
... HLVDIN. This gives users flexibility because it allows them to configure the High/Low-Voltage Detect interrupt to occur at any voltage in the valid operating range HLVDL3:HLVDL0 HLVDEN Internal Voltage Reference 1.2V Typical Preliminary the HLVDL3:HLVDL0 bits HLVDCON Register VDIRMAG Set HLVDIF © 2007 Microchip Technology Inc. ...
Page 189
... DD HLVDIF Enable HLVD IRVST Internal Reference is stable © 2007 Microchip Technology Inc. PIC18F2450/4450 Depending on the application, the HLVD module does not need to be operating constantly. To decrease the current requirements, the HLVD circuitry may only need to be enabled for short periods where the voltage is checked ...
Page 190
... HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists FIGURE 17-4: TYPICAL HIGH/LOW-VOLTAGE DETECT APPLICATION Legend HLVD trip point Minimum valid device B operating voltage Preliminary V HLVD HLVDIF cleared in software V HLVD Time © 2007 Microchip Technology Inc. ...
Page 191
... IPR2 OSCFIP — Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module. © 2007 Microchip Technology Inc. PIC18F2450/4450 17.7 Effects of a Reset A device Reset forces all registers to their Reset state. This forces the HLVD module to be turned off. ...
Page 192
... PIC18F2450/4450 NOTES: DS39760C-page 190 Preliminary © 2007 Microchip Technology Inc. ...
Page 193
... Section 2.0 “Oscillator Configurations”. A complete discussion of device Resets and interrupts is available in previous sections of this data sheet. © 2007 Microchip Technology Inc. PIC18F2450/4450 In addition to their Power-up and Oscillator Start-up Timers provided for Resets, PIC18F2450/4450 devices have a Watchdog Timer, which is either permanently enabled via the Configuration bits or software controlled (if configured as disabled) ...
Page 194
... See Register 18-13 and Register 18-14 for device ID values. DEVID registers are read-only and cannot be programmed by the user. 2: Available only on PIC18F4450 devices in 44-pin TQFP packages. Always leave this bit clear in all other devices. DS39760C-page 192 Programming the Configuration registers is done in a manner similar to programming the Flash memory. The WR bit in the EECON1 register starts a self-timed write to the Configuration register ...
Page 195
... Divide by 5 (20 MHz oscillator input) 011 = Divide by 4 (16 MHz oscillator input) 010 = Divide by 3 (12 MHz oscillator input) 001 = Divide MHz oscillator input) 000 = No prescale (4 MHz oscillator input drives PLL directly) © 2007 Microchip Technology Inc. PIC18F2450/4450 R/P-0 R/P-0 R/P-1 CPUDIV1 ...
Page 196
... EC modes. The USB module uses the indicated XT oscillator as its clock source whenever the microcontroller uses the internal oscillator. DS39760C-page 194 U-0 R/P-0 R/P-1 (1) (1) — FOSC3 FOSC2 U = Unimplemented bit, read as ‘0’ Unchanged from programmed state (1) Preliminary © 2007 Microchip Technology Inc. R/P-1 R/P-1 (1) (1) FOSC1 FOSC0 bit 0 ...
Page 197
... PWRTEN: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled Note 1: See Section 21.0 “Electrical Characteristics” for the specifications. 2: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently controlled. © 2007 Microchip Technology Inc. PIC18F2450/4450 R/P-1 R/P-1 R/P-1 (1) (1) (2) ...
Page 198
... WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) DS39760C-page 196 R/P-1 R/P-1 R/P-1 WDTPS3 WDTPS2 WDTPS1 U = Unimplemented bit, read as ‘0’ Unchanged from programmed state Preliminary R/P-1 R/P-1 WDTPS0 WDTEN bit 0 © 2007 Microchip Technology Inc. ...
Page 199
... PBADEN: PORTB A/D Enable bit (Affects ADCON1 Reset state. ADCON1 controls PORTB<4:0> pin configuration PORTB<4:0> pins are configured as analog input channels on Reset 0 = PORTB<4:0> pins are configured as digital I/O on Reset bit 0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC18F2450/4450 U-0 U-0 R/P-0 — ...
Page 200
... Unimplemented: Read as ‘0’ bit 0 STVREN: Stack Full/Underflow Reset Enable bit 1 = Stack full/underflow will cause Reset 0 = Stack full/underflow will not cause Reset Note 1: Available only on PIC18F4450 devices in 44-pin TQFP packages. Always leave this bit clear in all other devices. DS39760C-page 198 U-0 R/P-0 R/P-1 (1) — ...