PIC18F2450-I/ML Microchip Technology, PIC18F2450-I/ML Datasheet - Page 168

• Manufacturer Part Number: PIC18F2450-I/ML
• Description: IC PIC MCU FLASH 8KX16 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2450-I/ML

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: UART/USART, USB
• Number Of I /o: 23
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC18
• No. Of I/o's: 23
• Ram Memory Size: 768Byte
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• A/d Bit Size: 10 bit
• A/d Channels Available: 10
• Height: 0.88 mm
• Length: 6 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 6 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFNDM163025 - PIC DEM FULL SPEED USB DEMO BRD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F2450/4450
FIGURE 15-7:
TABLE 15-6:
DS39760D-page 166
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCON
SPBRGH
SPBRG
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note:
Name
RX (pin)
Rcv Shift Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word
causing the OERR (Overrun Error) bit to be set.
EUSART Receive Register
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
ABDOVF
SPEN
CSRC
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7
—
—
—
ASYNCHRONOUS RECEPTION
Start
bit
bit 0
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
bit 1
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
—
bit 7/8
Stop
INT0IE
CREN
SYNC
SCKP
bit
Bit 4
TXIF
TXIE
TXIP
Word 1
RCREG
Start
bit
ADDEN
SENDB
bit 0
BRG16
RBIE
Bit 3
—
—
—
TMR0IF
CCP1IE
CCP1IP
CCP1IF
bit 7/8
BRGH
FERR
Word 2
RCREG
Bit 2
—
Stop
bit
TMR2IF
TMR2IE
TMR2IP
INT0IF
OERR
TRMT
Start
WUE
© 2008 Microchip Technology Inc.
Bit 1
bit
TMR1IF
TMR1IE
TMR1IP
ABDEN
RX9D
TX9D
bit 7/8
RBIF
Bit 0
Stop
bit
on Page:
Values
Reset
49
51
51
51
51
50
51
51
50
50