PIC24HJ32GP204-I/PT Microchip Technology, PIC24HJ32GP204-I/PT Datasheet
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... PIC24HJ32GP202/204 and © 2007 Microchip Technology Inc. PIC24HJ16GP304 Data Sheet High-Performance, 16-bit Microcontrollers Preliminary DS70289A ...
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... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... On-Chip Flash and SRAM: • Flash program memory ( Kbytes) • Data SRAM (2 Kbytes) • Boot and General Security for Program Flash © 2007 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 Digital I/O: • Peripheral Pin Select Functionality • programmable digital I/O pins • ...
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... Fully static design • 3.3V (±10%) operating voltage • Industrial and extended temperature • Low-power consumption Packaging: • 28-pin SDIP/SOIC/QFN-S • 44-pin QFN/TQFP Note: See the device variant tables for exact peripheral features per device. Preliminary © 2007 Microchip Technology Inc. ...
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... The device names, pin counts, memory sizes and peripheral availability of each family are listed below, followed by their pinout diagrams. TABLE 1: PIC24HJ32GP202/204 AND PIC24HJ16GP304 CONTROLLER FAMILIES Device PIC24HJ32GP202 28 32 PIC24HJ32GP204 44 32 PIC24HJ16GP304 44 16 Note 1: Only 2 out of 3 timers are Remappable © 2007 Microchip Technology Inc. ...
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... DS70289A-page 4 MCLR +/CN2/RA0 -/CN3/RA1 AN9/RP15/CN11/RB15 3 26 AN10/RP14/CN12/RB14 4 25 AN11/RP13/CN13/RB13 5 24 AN12/RP12/CN14/RB12 6 23 PGEC2/TMS/RP11/CN15/RB11 PGED2/TDI/RP10/CN16 / RB10 CAP DDCORE TDO/SDA1/RP9/CN21/RB9 11 18 TCK/SCL1/RP8/CN22/RB8 INT0/RP7/CN23/RB7 PGEC3/ASCL1/RP6/CN24/RB6 AN11/RP13/CN13/RB13 1 21 AN12/RP12/CN14/RB12 2 20 PGEC2/TMS/RP11/CN15/RB11 3 19 PIC24HJ32GP202 PGED2/TDI/RP10/CN16/RB10 CAP 6 16 Vss 7 TDO/SDA1/RP9/CN21/RB9 Preliminary DDCORE © 2007 Microchip Technology Inc. ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 Pin Diagrams (Continued) 44-Pin TQFP AN4/RP2/CN6/RB2 AN5/RP3/CN7/RB3 AN6/RP16/CN8/RC0 AN7/RP17/CN9/RC1 AN8/RP18/CN10/RC2 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 TDO/RA8 SOSCI/RP4/CN1/RB4 © 2007 Microchip Technology Inc. 11 AN11/RP13/CN13/RB13 AN12/RP12/CN14/RB12 25 9 PGEC2/RP11/CN15/RB11 8 26 PGED2/RP10/CN16/RB10 CAP PIC24HJ32GP204 PIC24HJ16GP304 5 29 RP25/CN19/RC9 4 RP24/CN20/RC8 RP23/CN17/RC7 2 32 RP22/CN18/RC6 1 33 SDA1/RP9/CN21/RB9 Preliminary /V DDCORE DS70289A-page 5 ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 Pin Diagrams (Continued) 44-Pin TQFP AN4/RP2/CN6/RB2 AN5/RP3/CN7/RB3 AN6/RP16/CN8/RC0 AN7/RP17/CN9/RC1 AN8/RP18/CN10/RC2 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 TDO/RA8 SOSCI/RP4/CN1/RB4 DS70289A-page 6 11 AN11/RP13/CN13/RB13 AN12/RP12/CN14/RB12 25 9 PGEC2/RP11/CN15/RB11 8 26 PGED2/RP10/CN16/RB10 CAP PIC24HJ32GP204 PIC24HJ16GP304 5 29 RP25/CN19/RC9 4 30 RP24/CN20/RC8 3 RP23/CN17/RC7 RP22/CN18/RC6 1 SDA1/RP9/CN21/RB9 33 Preliminary /V DDCORE © 2007 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2007 Microchip Technology Inc. Preliminary DS70289A-page 7 ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 NOTES: DS70289A-page 8 Preliminary © 2007 Microchip Technology Inc. ...
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... Family Reference Manual”. This document contains device-specific information for the following devices: • PIC24HJ32GP202 • PIC24HJ32GP204 • PIC24HJ16GP304 Figure 1-1 shows a general block diagram of the core and peripheral modules in the PIC24HJ32GP202/204 and PIC24HJ16GP304 family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams ...
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... DS70289A-page 10 Data Bus Data Latch X RAM Address Loop Latch Control Logic 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg Multiplier Register Array Divide Support 16-bit ALU MCLR UART1 CNx SPI1 I2C1 Preliminary PORTA PORTB 16 Remappable Pins © 2007 Microchip Technology Inc. ...
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... Analog REF Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels © 2007 Microchip Technology Inc. Description Analog input channels. External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode ...
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... Positive supply for analog modules. Master Clear (Reset) input. This pin is an active-low Reset to the device. Ground reference for analog modules. Positive supply for peripheral logic and I/O pins. Analog = Analog input I = Input Preliminary O = Output P = Power © 2007 Microchip Technology Inc. ...
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... operations to be executed in a single cycle. A block diagram of the CPU is shown in Figure 2-1, and the programmer’s model for the PIC24HJ32GP202/ 204 and PIC24HJ16GP304 is shown in Figure 2-2. © 2007 Microchip Technology Inc. 2.1 Data Addressing Overview The data space can be linearly addressed as 32K words or 64 Kbytes using an Address Generation Unit (AGU) ...
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... Control Signals to Various Blocks DS70289A-page 14 X Data Bus Data Latch PCH PCL X RAM Address Loop Control Latch Logic 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg Multiplier Register Array Divide Support Preliminary 16-bit ALU 16 To Peripheral Modules © 2007 Microchip Technology Inc. ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 FIGURE 2-2: PIC24HJ32GP202/204 AND PIC24HJ16GP304 PROGRAMMER’S MODEL PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG — — — — — — SRH © 2007 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 W12 W13 W14/Frame Pointer W15/Stack Pointer ...
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... The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). DS70289A-page 16 U-0 U-0 — — (2) R-0 R/W-0 R/W Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (2) Preliminary U-0 U-0 R/W-0 — — DC bit 8 R/W-0 R/W bit 0 © 2007 Microchip Technology Inc. ...
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... Program space visible in data space 0 = Program space not visible in data space bit 1-0 Unimplemented: Read as ‘0’ Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. © 2007 Microchip Technology Inc. U-0 U-0 U-0 — ...
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... The shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. A positive value shifts the operand right. and a negative value shifts the operand left. A value of ‘0’ does not modify the operand. Preliminary © 2007 Microchip Technology Inc. ...
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... Flash Memory (11264 instructions) Unimplemented (Read ‘0’s) Reserved Device Configuration Registers Reserved DEVID (2) © 2007 Microchip Technology Inc. 3.1 Program Address Space The program PIC24HJ32GP202/204 and devices is 4M instructions. The space is addressable by a 24-bit value derived either from the 23-bit Program ...
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... Interrupt Service Routines (ISRs). Section 6.1 “Inter- rupt Vector Table” provides a more detailed discus- sion of the interrupt vector tables. least significant word Instruction Width Preliminary and PIC24HJ16GP304 PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006 © 2007 Microchip Technology Inc. ...
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... Data byte writes only write to the corre- sponding side of the array or register that matches the byte address. © 2007 Microchip Technology Inc. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word opera- tions, or when translating from 8-bit MCU code ...
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... Optionally Mapped into Program Memory 0xFFFF DS70289A-page 22 LSB 16 bits Address MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x0FFE 0x1000 0x1FFE 0x2000 0x8000 X Data Unimplemented (X) 0xFFFE Preliminary 8 Kbyte Near data space © 2007 Microchip Technology Inc. ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 © 2007 Microchip Technology Inc. Preliminary DS70289A-page 23 ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 DS70289A-page 24 Preliminary © 2007 Microchip Technology Inc. ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 © 2007 Microchip Technology Inc. Preliminary DS70289A-page 25 ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 DS70289A-page 26 Preliminary © 2007 Microchip Technology Inc. ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 © 2007 Microchip Technology Inc. Preliminary DS70289A-page 27 ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 DS70289A-page 28 Preliminary © 2007 Microchip Technology Inc. ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 © 2007 Microchip Technology Inc. Preliminary DS70289A-page 29 ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 DS70289A-page 30 Preliminary © 2007 Microchip Technology Inc. ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 © 2007 Microchip Technology Inc. Preliminary DS70289A-page 31 ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 DS70289A-page 32 Preliminary © 2007 Microchip Technology Inc. ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 © 2007 Microchip Technology Inc. Preliminary DS70289A-page 33 ...
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... Register Indirect Post-Modified • Register Indirect Pre-Modified • 5-bit or 10-bit Literal Note: Not all instructions support all the addressing modes given above. Individual instructions can support different subsets of these addressing modes. Preliminary © 2007 Microchip Technology Inc. addressing modes are ...
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... However, the 4-bit Wb (Register Offset) field is shared by both source and destination (but typically only used by one). © 2007 Microchip Technology Inc. Description The address of the file register is specified explicitly. The contents of a register are accessed directly. The contents of Wn forms the Effective Address (EA.) The contents of Wn forms the EA ...
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... TBLPAG<7:0> 0xxx xxxx xxxx xxxx xxxx xxxx TBLPAG<7:0> 1xxx xxxx xxxx xxxx xxxx xxxx PSVPAG<7:0> xxxx xxxx Preliminary © 2007 Microchip Technology Inc. <14:1> <0> 0 xxxx xxx0 Data EA<15:0> Data EA<15:0> (1) Data EA<14:0> xxx xxxx xxxx xxxx ...
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... Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. © 2007 Microchip Technology Inc. Program Counter 0 23 bits ...
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... TBLRDL.B (Wn<0> TBLRDL.B (Wn<0> TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in 0x800000 the user memory area. Preliminary © 2007 Microchip Technology Inc. ...
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... PSVPAG is mapped into the upper half of the data memory space... © 2007 Microchip Technology Inc. 24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with ‘1111 ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 NOTES: DS70289A-page 40 Preliminary © 2007 Microchip Technology Inc. ...
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... Using 1/0 Table Instruction User/Configuration Space Select © 2007 Microchip Technology Inc. RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user application can write program memory data either in and ‘blocks’ or ‘rows’ instructions (192 bytes time or a single program memory word, and erase program memory in blocks or ‘ ...
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... Flash in RTSP mode. A programming operation is nominally duration and the processor stalls (waits) until the oper- ation is finished. Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished. Preliminary © 2007 Microchip Technology Inc. ...
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... Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2007 Microchip Technology Inc. (1) U-0 U-0 — — (1) U-0 ...
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... NVMKEY<7:0>: Key Register (Write Only) bits DS70289A-page 44 U-0 U-0 U-0 — — — W-0 W-0 W-0 NVMKEY<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. U-0 U-0 — — bit 8 W-0 W-0 bit Bit is unknown ...
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... MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2007 Microchip Technology Inc. 4. Write the first 64 instructions from data RAM into the program memory buffers (see Example 4-2). 5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming ...
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... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the ; erase command is asserted Preliminary © 2007 Microchip Technology Inc. ...
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... DD Trap Conflict Illegal Opcode Uninitialized W Register Configuration Mismatch © 2007 Microchip Technology Inc. Any active source of Reset makes the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most and registers are unaffected by a Reset; their status is unknown on POR and unchanged by all other Resets ...
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... SWDTEN bit setting. DS70289A-page 48 (1) U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary R/W-0 R/W-0 CM VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... SWR (RCON<6>) WDTO (RCON<4>) SLEEP (RCON<3>) IDLE (RCON<2>) BOR (RCON<1>) POR (RCON<0>) Note: All Reset flag bits may be set or cleared by the user software. © 2007 Microchip Technology Inc. (1) Setting Event Trap conflict event Illegal opcode or uninitialized W register access Configuration mismatch MCLR Reset ...
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... RST T — RST T — RST T — RST T — RST is also applied to all returns from powered-down STARTUP Preliminary FSCM Notes Delay — FSCM FSCM LOCK FSCM — FSCM FSCM LOCK FSCM — 3 — 3 — 3 — 3 — 3 — 3 © 2007 Microchip Technology Inc. ...
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... FRC oscillator and the user application can switch to the desired crystal oscillator in the Trap Service Routine. © 2007 Microchip Technology Inc. 5.2.2.1 FSCM Delay for Crystal and PLL Clock Sources When the system clock source is provided by a crystal ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 NOTES: DS70289A-page 52 Preliminary © 2007 Microchip Technology Inc. ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 devices implement unique interrupts and 4 non- maskable traps. These are summarized in Table 6-1 and Table 6-2. © 2007 Microchip Technology Inc. 6.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located and after the IVT, as shown in Figure 6-1 ...
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... Note 1: See Table 6-1 for the list of implemented interrupt vectors. DS70289A-page 54 0x000000 0x000002 0x000004 0x000014 0x00007C Interrupt Vector Table (IVT) 0x00007E 0x000080 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 Alternate Interrupt Vector Table (AIVT) 0x00017C 0x00017E 0x000180 0x0001FE 0x000200 Preliminary © 2007 Microchip Technology Inc. (1) (1) ...
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... Microchip Technology Inc. AIVT Address Interrupt Source 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – Input Compare 1 0x000118 OC1 – Output Compare 1 0x00011A T1 – Timer1 0x00011C Reserved 0x00011E IC2 – Input Capture 2 0x000120 OC2 – ...
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... AIVT Address 0x000004 0x000104 0x000006 0x000106 0x000008 0x000108 0x00000A 0x00010A 0x00000C 0x00010C 0x00000E 0x00010E 0x000010 0x000110 0x000012 0x000112 Preliminary Interrupt Source Trap Source Reserved Oscillator Failure Address Error Stack Error Math Error Reserved Reserved Reserved © 2007 Microchip Technology Inc. ...
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... IECx The IEC registers maintain all the interrupt enable bits. These control bits are used individually to enable inter- rupts from the peripherals or external signals. © 2007 Microchip Technology Inc. 6.3.4 IPCx The IPC registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of the eight priority lev- els ...
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... The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15> DS70289A-page 58 (1) U-0 U-0 — — (3) R-0 R/W-0 R/W-0 ( Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (1) Preliminary U-0 U-0 R/W-0 — — DC bit 8 R/W-0 R/W bit 0 © 2007 Microchip Technology Inc. ...
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... CPU interrupt priority level less Note 1: For complete register details, see Register 2-2: “CORCON: CORE Control Register”. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. © 2007 Microchip Technology Inc. (1) U-0 U-0 U-0 — ...
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... Unimplemented: Read as ‘0’ DS70289A-page 60 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 MATHERR ADDRERR STKERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 U-0 OSCFAIL — bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2007 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 ...
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... Interrupt request has not occurred DS70289A-page 62 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF U-0 R/W-0 R/W-0 — T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1EIF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2007 Microchip Technology Inc. Preliminary DS70289A-page 63 ...
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... Interrupt request has not occurred DS70289A-page 64 U-0 U-0 U-0 — — — R/W-0 R/W-0 U-0 INT1IF CNIF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 MI2C1IF SI2C1IF bit Bit is unknown ...
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... Unimplemented: Read as ‘0’ bit 1 U1EIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 U-0 U-0 — ...
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... Interrupt request not enabled DS70289A-page 66 R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE U-0 R/W-0 R/W-0 — T1IE OC1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1EIE T3IE bit 8 R/W-0 R/W-0 IC1IE INT0IE bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2007 Microchip Technology Inc. Preliminary DS70289A-page 67 ...
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... Interrupt request not enabled DS70289A-page 68 U-0 U-0 U-0 — — — R/W-0 R/W-0 U-0 INT1IE CNIE — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 MI2C1IE SI2C1IE bit Bit is unknown ...
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... Bit is set bit 15-2 Unimplemented: Read as ‘0’ bit 1 U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 U-0 U-0 — ...
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... Interrupt is priority 1 000 = Interrupt source is disabled DS70289A-page 70 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R/W-0 R/W-0 OC1IP<2:0> bit 8 R/W-0 R/W-0 INT0IP<2:0> bit Bit is unknown ...
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... IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 U-0 — ...
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... Interrupt is priority 1 000 = Interrupt source is disabled DS70289A-page 72 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R/W-0 R/W-0 SPI1IP<2:0> bit 8 R/W-0 R/W-0 T3IP<2:0> bit Bit is unknown ...
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... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 — ...
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... Interrupt is priority 1 000 = Interrupt source is disabled DS70289A-page 74 R/W-0 U-0 U-0 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 SI2C1IP<2:0> bit Bit is unknown ...
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... Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. R/W-0 U-0 R/W-1 — U-0 U-0 R/W-1 — — ...
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... Unimplemented: Read as ‘0’ DS70289A-page 76 U-0 U-0 U-0 — — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown ...
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... U1EIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 U-0 U-0 — ...
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... Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 DS70289A-page 78 U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...
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... If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2007 Microchip Technology Inc. 6.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 NOTES: DS70289A-page 80 Preliminary © 2007 Microchip Technology Inc. ...
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... Secondary Oscillator SOSCO LPOSCEN SOSCI Note 1: See Figure 7-2 for PLL details © 2007 Microchip Technology Inc. • An internal FRC oscillator that can also be used with the PLL, thereby allowing full speed operation without any external clock generation hardware • Clock switching between various clock sources and • ...
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... This factor is selected using the PLLPOST<1:0> bits (CLKDIV<7:6>). ‘N2’ can and must be selected such that the PLL output frequency (F in the range of 12.5 MHz to 80 MHz, which generates PLL device operating speeds of 6.25-40 MIPS. Preliminary © 2007 Microchip Technology Inc. is divided OSC ). ...
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... Fast RC Oscillator (FRC) Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. © 2007 Microchip Technology Inc. ’, • If PLLDIV<8:0> = 0x1E, then M = 32. This yields a IN VCO output 160 MHz, which is within the 100 MHz to 200 MHz range, which is needed. • ...
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... Unimplemented: Read as ‘0’ DS-70289A-page 84 R-0 U-0 R/W-y — U-0 R/C-0 U-0 — CF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R/W-y R/W-y NOSC<2:0> bit 8 R/W-0 R/W-0 LPOSCEN OSWEN bit Bit is unknown ...
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... REGISTER 7-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete © 2007 Microchip Technology Inc. Preliminary DS-70289A-page 85 ...
Page 88
... This bit is cleared when the ROI bit is set and an interrupt occurs. DS-70289A-page 86 R/W-0 R/W-0 R/W-1 (1) DOZEN R/W-0 R/W-0 R/W-0 PLLPRE<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary © 2007 Microchip Technology Inc. R/W-0 R/W-0 FRCDIV<2:0> bit 8 R/W-0 R/W-0 bit Bit is unknown ...
Page 89
... PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) 000000000 = 2 000000001 = 3 000000010 = 4 • • • 000110000 = 50 (default) • • • 111111111 = 513 © 2007 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ...
Page 90
... Center frequency – 12% (6.49 MHz) DS-70289A-page 88 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 TUN<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 bit Bit is unknown ...
Page 91
... The clock switching hardware compares the COSC status bits with the new value of the NOSC control bits. If both of them are the same, the clock switch is a redundant operation. In this © 2007 Microchip Technology Inc. case, the OSWEN bit is cleared automatically and the clock switch is aborted. 2. ...
Page 92
... PIC24HJ32GP202/204 and PIC24HJ16GP304 NOTES: DS-70289A-page 90 Preliminary © 2007 Microchip Technology Inc. ...
Page 93
... EXAMPLE 8-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2007 Microchip Technology Inc. 8.2 Instruction-Based Power-Saving Modes PIC24HJ32GP202/204 and PIC24HJ16GP304 devices and have two special power-saving modes that are entered through the execution of a special PWRSAV instruction ...
Page 94
... Similarly PMD bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control regis- ters are already configured to enable mod- ule operation). Preliminary © 2007 Microchip Technology Inc. are eight possible ...
Page 95
... CK WR Port Data Latch Read LAT Read Port © 2007 Microchip Technology Inc. When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin and can be read, but the output driver for the parallel port bit is disabled ...
Page 96
... CNPU2 registers, which contain the control bits for each of the CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. Note: Pull-ups on change notification pins should always be disabled when the port pin is configured as a digital output. Preliminary PIC24HJ32GP202/204 and © 2007 Microchip Technology Inc. ...
Page 97
... These modules include I A similar requirement excludes all modules with analog inputs, such as the Analog-to-Digital Converter (ADC). © 2007 Microchip Technology Inc. Remappable peripherals are not associated with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be used. In ...
Page 98
... RPINR7 IC2 RPINR7 IC7 RPINR10 IC8 RPINR10 OCFA RPINR11 U1RX RPINR18 U1CTS RPINR18 SDI1 RPINR20 SCK1IN RPINR20 SS1IN RPINR21 Preliminary Configuration Bits INT1R[4:0] INT2R[4:0] T2CKR[4:0] T3CKR[4:0] IC1R[4:0] IC2R[4:0] IC7R[4:0] IC8R[4:0] OCFAR[4:0] U1RXR[4:0] U1CTSR[4:0] SDI1R[4:0] SCK1R[4:0] SS1R[4:0] © 2007 Microchip Technology Inc. ...
Page 99
... SDO1 SCK1OUT SS1OUT OC1 OC2 © 2007 Microchip Technology Inc. value of the bit field corresponds to one of the periph- erals, and that peripheral’s output is mapped to the pin (see Table 9-2 and Figure 9-3). The list of peripherals for output mapping also includes a null value of 00000 because of the mapping tech- nique ...
Page 100
... Because the unlock sequence is timing-critical, it must be executed as an assembly-language routine, in the same manner as changes configuration. If the bulk of the application is written another high-level language, the unlock sequence should be performed by writing inline assembly. Preliminary © 2007 Microchip Technology Inc. the proper peripheral to the oscillator ...
Page 101
... UART1. The fol- lowing input and output functions are used: • Input Functions: U1RX, U1CTS • Output Functions: U1TX, U1RTS © 2007 Microchip Technology Inc. 9.5 Peripheral Pin Select Registers The PIC24HJ32GP202/204 and PIC24HJ16GP304 devices implement 17 registers for remappable periph- eral configuration: • ...
Page 102
... Unimplemented: Read as ‘0’ DS70289A-page 100 R/W-1 R/W-1 R/W-1 INT1R<4:0> U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R/W-1 R/W-1 bit 8 U-0 U-0 — — bit Bit is unknown ...
Page 103
... INT2R<4:0>: Assign External Interrupt 2 (INTR2) to the corresponding RPn pin 11111 = Input tied to Vss 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 INT2R< ...
Page 104
... Input tied to RP1 00000 = Input tied to RP0 DS70289A-page 102 R/W-1 R/W-1 R/W-1 T3CKR<4:0> R/W-1 R/W-1 R/W-1 T2CKR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown ...
Page 105
... T2CKR<4:0>: Assign Timer2 External Clock (T2CK) to the Corresponding RPn pin 11111 = Input tied to Vss 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. R/W-1 R/W-1 R/W-1 IC2R<4:0> R/W-1 R/W-1 R/W-1 IC1R< ...
Page 106
... Input tied to RP1 00000 = Input tied to RP0 DS70289A-page 104 R/W-1 R/W-1 R/W-1 IC8R<4:0> R/W-1 R/W-1 R/W-1 IC7R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown ...
Page 107
... OCFAR<4:0>: Assign Output Capture A (OCFA) to the corresponding RPn pin 11111 = Input tied to Vss 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 OCFAR< ...
Page 108
... Input tied to RP1 00000 = Input tied to RP0 DS70289A-page 106 R/W-1 R/W-1 R/W-1 U1CTSR<4:0> R/W-1 R/W-1 R/W-1 U1RXR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown ...
Page 109
... SDI1R<4:0>: Assign SPI 1 Data Input (SDI1) to the corresponding RPn pin 11111 = Input tied to Vss 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. R/W-1 R/W-1 R/W-1 SCK1R<4:0> R/W-1 R/W-1 R/W-1 SDI1R< ...
Page 110
... Input tied to RP0 DS70289A-page 108 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 SS1R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-1 R/W-1 bit Bit is unknown ...
Page 111
... RP3R<4:0>: Peripheral Output Function is Assigned to RP3 Output Pin (see Table 9-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin (see Table 9-2 for peripheral function numbers) © 2007 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP1R<4:0> R/W-0 R/W-0 R/W-0 RP0R< ...
Page 112
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 RP7R<4:0> R/W-0 R/W-0 R/W-0 RP6R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 ...
Page 113
... RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin (see Table 9-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP10R<4:0>: Peripheral Output Function is Assigned to RP10 Output Pin (see Table 9-2 for periph- eral function numbers) © 2007 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP9R<4:0> R/W-0 R/W-0 R/W-0 RP8R< ...
Page 114
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 RP15R<4:0> R/W-0 R/W-0 R/W-0 RP14R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 ...
Page 115
... RP19R<4:0>: Peripheral Output Function is Assigned to RP19 Output Pin (see Table 9-2 for periph- eral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP18R<4:0>: Peripheral Output Function is Assigned to RP18 Output Pin (see Table 9-2 for periph- eral function numbers) © 2007 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP17R<4:0> R/W-0 R/W-0 R/W-0 RP16R< ...
Page 116
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 RP23R<4:0> R/W-0 R/W-0 R/W-0 RP22R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 ...
Page 117
... RP25R<4:0>: Peripheral Output Function is Assigned to RP25 Output Pin (see Table 9-2 for periph- eral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP24R<4:0>: Peripheral Output Function is Assigned to RP24 Output Pin (see Table 9-2 for periph- eral function numbers) © 2007 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP25R<4:0> R/W-0 R/W-0 R/W-0 RP24R< ...
Page 118
... PIC24HJ32GP202/204 and PIC24HJ16GP304 NOTES: DS70289A-page 116 Preliminary © 2007 Microchip Technology Inc. ...
Page 119
... T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2007 Microchip Technology Inc. Figure 10-1 shows a block diagram of the 16-bit timer module. To configure Timer1 for operation: and 1. Set the TON bit (= 1) in the T1CON register. 2. Select the timer prescaler ratio using the TCKPS< ...
Page 120
... Unimplemented: Read as ‘0’ DS70289A-page 118 U-0 U-0 — — R/W-0 U-0 R/W-0 — TSYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 U-0 TCS — bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 121
... Timer2 clock and gate inputs are used for the 32-bit timer modules, but an interrupt is gener- ated with the Timer3 interrupt flags. © 2007 Microchip Technology Inc. 11.1 32-bit Operation To configure the Timer2/3 feature for 32-bit operation: and 1 ...
Page 122
... The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register. 2: The ADC event trigger is available only on Timer2/3. DS70289A-page 120 (1) 1x Gate Sync PR2 PR3 Comparator LSb TMR3 TMR2 TMR3HLD 16 Preliminary TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TGATE TCS Sync © 2007 Microchip Technology Inc. ...
Page 123
... PIC24HJ32GP202/204 and PIC24HJ16GP304 FIGURE 11-2: TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal © 2007 Microchip Technology Inc. 1x Gate Sync TMR2 Sync Comparator PR2 Preliminary TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TCS TGATE DS70289A-page 121 ...
Page 124
... In 32-bit mode, T3CON control bits do not affect 32-bit timer operation. DS70289A-page 122 U-0 U-0 — — R/W-0 R/W-0 (1) T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) ) Preliminary U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 125
... External clock from pin T3CK (on the rising edge Internal clock (F CY bit 0 Unimplemented: Read as ‘0’ Note 1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timer3 operation; all timer functions are set through T2CON. © 2007 Microchip Technology Inc. U-0 U-0 (1) — — R/W-0 U-0 (1) — ...
Page 126
... PIC24HJ32GP202/204 and PIC24HJ16GP304 NOTES: DS70289A-page 124 Preliminary © 2007 Microchip Technology Inc. ...
Page 127
... Mode Select ICOV, ICBNE (ICxCON<4:3>) ICxCON System Bus Note: An ‘x’ signal, register or bit name denotes the number of the capture channel. © 2007 Microchip Technology Inc. • Prescaler Capture Event modes: - Capture timer value on every 4th rising edge of input at ICx pin and ...
Page 128
... DS-70289A-page 126 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 129
... OCM bits to ‘100’. Disabling and re-enabling the timer, and clearing © 2007 Microchip Technology Inc. the TMRy register, are not required, but may be advantageous for defining a pulse from a known event time boundary ...
Page 130
... See Example 13-1 for PWM mode timing details. Table 13-1 shows an example of PWM frequencies and resolutions for a device operating at 10 MIPS log 10 F PWM bits log (2) 10 Preliminary © 2007 Microchip Technology Inc. • (Timer Prescale Value) CY ...
Page 131
... Period Register Value FFFFh Resolution (bits) 16 TABLE 13-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MIPS (F PWM Frequency 76 Hz Timer Prescaler Ratio 8 Period Register Value FFFFh Resolution (bits) 16 © 2007 Microchip Technology Inc. • (Timer2 Prescale Value) /F )/log 2) bits PWM 10 2) bits 122 Hz 977 ...
Page 132
... OCFA pin controls OC1-OC2 channels. 3: TMR2/TMR3 can be selected via OCTSEL(OCxOCN<3>) bit. DS70289A-page 130 Set Flag bit (1) OCxIF S Q Output Logic R Output Enable 3 OCM2:OCM0 Mode Select 0 1 Period match signals (3) from time bases Preliminary (1) OCx OCFA © 2007 Microchip Technology Inc. ...
Page 133
... Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled © 2007 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 134
... PIC24HJ32GP202/204 and PIC24HJ16GP304 NOTES: DS70289A-page 132 Preliminary © 2007 Microchip Technology Inc. ...
Page 135
... The module will not respond to SCL transitions while SPIROV is ‘1’, effec- tively disabling the module until SPIxBUF is read by user software. © 2007 Microchip Technology Inc. 14.3 Transmit Operations Transmit writes are also double-buffered. The user appli- cation writes to SPIxBUF ...
Page 136
... SDOx bit 0 SDIx SPIxSR Transfer SPIxRXB SPIxBUF Read SPIxBUF DS70289A-page 134 1:1 to 1:8 Secondary Prescaler Select Edge Shift Control Transfer SPIxTXB Write SPIxBUF 16 Internal Data Bus Preliminary 1:1/4/16/64 Primary F CY Prescaler SPIxCON1<1:0> SPIxCON1<4:2> Enable Master Clock © 2007 Microchip Technology Inc. ...
Page 137
... User application must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF. FIGURE 14-3: SPI MASTER AND FRAME MASTER CONNECTION DIAGRAM PIC24H FIGURE 14-4: SPI MASTER AND FRAME SLAVE CONNECTION DIAGRAM PIC24H © 2007 Microchip Technology Inc. PROCESSOR 2 (SPI Slave) SDOx SDIx Serial Receive Buffer SDIx SDOx LSb ...
Page 138
... Preliminary 4:1 6:1 8:1 6666.67 5000 1666.67 1250 625 416.67 312.50 104.17 78.125 833 625 313 208 156 © 2007 Microchip Technology Inc. ...
Page 139
... SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB © 2007 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 140
... The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). DS70289A-page 138 R/W-0 R/W-0 R/W-0 DISSCK DISSDO MODE16 R/W-0 R/W-0 R/W-0 SPRE<2:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 (1) SMP CKE bit 8 R/W-0 R/W-0 PPRE<1:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 141
... PPRE<1:0>: Primary Prescale bits (Master mode Primary prescale 1 Primary prescale 4 Primary prescale 16 Primary prescale 64:1 Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). © 2007 Microchip Technology Inc. Preliminary DS70289A-page 139 ...
Page 142
... DS70289A-page 140 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 U-0 FRMDLY — bit Bit is unknown ...
Page 143
... I C master operation with 7- or 10-bit address For details about the communication sequence in each of these modes, refer to the “PIC24H Family Reference Manual”. © 2007 Microchip Technology Inc Registers I2CxCON and I2CxSTAT are control and status registers, respectively. The I2CxCON register is readable and writable ...
Page 144
... Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSb Reload Control Preliminary Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2007 Microchip Technology Inc. ...
Page 145
... The control bit IPMIEN enables the module to support the Intelligent Peripheral Management Interface (IPMI). When this bit is set, the module accepts and acts upon all addresses. © 2007 Microchip Technology Inc. 15.8 General Call Address Support The general call address can address all devices. ...
Page 146
... When the ACTI2C bit in the FPOR configura- tion register is set to ‘1‘, the module uses the SDAx/ SCLx pins. If the ALTI2C bit is ‘0‘, the module uses the ASDAx/ASCLx pins. Preliminary © 2007 Microchip Technology Inc port to its Idle state. ...
Page 147
... General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I Used in conjunction with SCLREL bit Enable software or receive clock stretching 0 = Disable software or receive clock stretching © 2007 Microchip Technology Inc. R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN A10M ...
Page 148
... Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence Start condition not in progress DS70289A-page 146 2 C master, applicable during master receive master Hardware clear at end of eighth bit of master receive data byte master master master) Preliminary © 2007 Microchip Technology Inc. ...
Page 149
... Hardware clear at device address match. Hardware set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. © 2007 Microchip Technology Inc. U-0 U-0 R/C-0 HS — — ...
Page 150
... I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. DS70289A-page 148 2 C slave device address byte. Preliminary © 2007 Microchip Technology Inc. ...
Page 151
... AMSKx: Mask for Address bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position © 2007 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 152
... PIC24HJ32GP202/204 and PIC24HJ16GP304 NOTES: DS70289A-page 150 Preliminary © 2007 Microchip Technology Inc. ...
Page 153
... UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator Hardware Flow Control UART Receiver UART Transmitter © 2007 Microchip Technology Inc. • Fully Integrated Baud Rate Generator with 16-bit prescaler • Baud rates ranging from 1 Mbps to 15 Mbps at 16 MIPS • 4-deep first-in-first-out (FIFO) Transmit Data ...
Page 154
... BRG timer to be reset (cleared). This ensures the BRG does not wait for a timer overflow before generating the new baud rate. Desired Baud Rate Preliminary /(16 * 65536). UART BAUD RATE WITH BRGH = • (BRGx + – • Baud Rate denotes the instruction cycle clock /2). OSC /4 CY © 2007 Microchip Technology Inc. ...
Page 155
... Write 0x55 to UxTXREG, which loads the Sync character into the transmit FIFO. After the Break has been sent, the UTXBRK bit is reset by hard- ware. The Sync character now starts transmit- ting. © 2007 Microchip Technology Inc. 16.5 Receiving in 8-bit or 9-bit Data Mode 1. ...
Page 156
... DS70289A-page 154 MODE REGISTER x R/W-0 R/W-0 U-0 (1) IREN RTSMD — R/W-0 R/W-0 R/W-0 URXINV BRGH U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 UEN<1:0> bit 8 R/W-0 R/W-0 PDSEL<1:0> STSEL bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 157
... STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1: This feature is only available for the 16x BRG mode (BRGH = 0). © 2007 Microchip Technology Inc. MODE REGISTER (CONTINUED) x Preliminary DS70289A-page 155 ...
Page 158
... STATUS AND CONTROL REGISTER x U-0 R/W-0 HC R/W-0 — UTXBRK UTXEN R-1 R-0 RIDLE PERR FERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R-0 R-1 UTXBF TRMT bit 8 R-0 R/C-0 R-0 OERR URXDA bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 159
... Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1). © 2007 Microchip Technology Inc. STATUS AND CONTROL REGISTER (CONTINUED) x Preliminary DS70289A-page 157 ...
Page 160
... PIC24HJ32GP202/204 and PIC24HJ16GP304 NOTES: DS70289A-page 158 Preliminary © 2007 Microchip Technology Inc. ...
Page 161
... Refer to the device data sheet for fur- ther details. A block diagram of ADC for PIC24HJ16GP304 and PIC24HJ32GP204 devices is shown in Figure 17-1. A block diagram of the ADC for the PIC24HJ32GP202 device is shown in Figure 17-2. 17.2 ...
Page 162
... PIC24HJ32GP202/204 and PIC24HJ16GP304 FIGURE 17-1: ADC1 MODULE BLOCK DIAGRAM FOR PIC24HFJ16GP304 AND PIC24HJ32GP204 DEVICES ( REF ( REF AN0 AN0 AN3 AN6 AN9 V REF AN1 AN1 AN4 AN7 AN10 V REF AN2 AN2 AN5 AN8 AN11 V REF 00000 00001 00010 00011 AN3 00100 AN4 ...
Page 163
... AN9 01010 AN10 01011 AN11 01100 AN12 V REF AN1 Note inputs may be multiplexed with other analog inputs. REF REF 2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation. © 2007 Microchip Technology Inc (2) CH1 ADC1 S Conversion Result + (2) CH2 S/H ...
Page 164
... REFL REFH REFL + V + REFL 1024 1024 AD1CON3<5:0> 6 ADC Conversion Clock Multiplier 5,..., 64 F when the PLL is enabled. If the PLL is not used, OSC OSC Preliminary V REFH ) 1023 * (V – REFH REFL V + REFL 1024 (V – INH INL AD1CON3<15> equal OSC © 2007 Microchip Technology Inc. ...
Page 165
... SIMSAM: Simultaneous Sample Select bit (applicable only when CHPS<1:0> 1x) When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’ Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or Samples CH0 and CH1 simultaneously (when CHPS<1:0> Samples multiple channels individually in sequence © 2007 Microchip Technology Inc. U-0 U-0 — — ...
Page 166
... Automatically set by hardware when ADC conversion is complete. Software can write ‘0’ to clear DONE status (software not allowed to write ‘1’). Clearing this bit will NOT affect any operation in progress. Automatically cleared by hardware at start of a new conversion. DS70289A-page 164 Preliminary © 2007 Microchip Technology Inc. ...
Page 167
... Always starts filling buffer from the beginning bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses channel input selects for Sample A on first sample and Sample B on next sample 0 = Always uses channel input selects for Sample A © 2007 Microchip Technology Inc. U-0 U-0 — — ...
Page 168
... T · (ADCS<7:0> · 00000000 = T · (ADCS<7:0> · DS70289A-page 166 R/W-0 R/W-0 R/W-0 SAMC<4:0> R/W-0 R/W-0 R/W-0 ADCS<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared = Preliminary © 2007 Microchip Technology Inc. R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown ...
Page 169
... Reserved 00 = Reserved If AD12B = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 10 = Reserved 01 = CH1, CH2, CH3 negative input CH1, CH2, CH3 negative input is V PIC24HJ32GP204 and PIC24HJ16GP304 devices only: If AD12B = Reserved 10 = Reserved 01 = Reserved 00 = Reserved If AD12B = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 ...
Page 170
... Reserved 00 = Reserved If AD12B = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 10 = Reserved 01 = CH1, CH2, CH3 negative input CH1, CH2, CH3 negative input is V PIC24HJ32GP204 and PIC24HJ16GP304 devices only: If AD12B = Reserved 10 = Reserved 01 = Reserved 00 = Reserved If AD12B = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 ...
Page 171
... Channel 0 negative input is AN1 0 = Channel 0 negative input is V bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 CH0SB<4:0>: Channel 0 Positive Input Select for Sample B bits PIC24HJ32GP204 and PIC24HJ16GP304 devices only: 01100 = Channel 0 positive input is AN12 • • • 00010 = Channel 0 positive input is AN2 ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 REGISTER 17-5: AD1CHS0: ADC1 INPUT CHANNEL 0 SELECT REGISTER (CONTINUED) bit 4-0 CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits PIC24HJ32GP204 and PIC24HJ16GP304 devices only: 01100 = Channel 0 positive input is AN12 • • • 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 ...
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... Port pin in Analog mode, port read input disabled, ADC samples pin voltage Note 1: On devices without nine analog inputs, all PCFG bits are R/W. However, PCFG bits are ignored on ports without a corresponding input on device. © 2007 Microchip Technology Inc. U-0 U-0 U-0 ...
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... PIC24HJ32GP202/204 and PIC24HJ16GP304 NOTES: DS70289A-page 172 Preliminary © 2007 Microchip Technology Inc. ...
Page 175
... FUID2 0xF80016 FUID3 Note 1: These reserved bits read as ‘1’ and must be programmed as ‘1’. © 2007 Microchip Technology Inc. 18.1 Configuration Bits The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’), to select and various device configurations. These bits are mapped starting at program memory location 0xF80000 ...
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... Description Boot Segment Program Flash Write Protection 1 = Boot segment may be written 0 = Boot segment is write-protected PIC24HJ32GP202 and PIC24HJ32GP204 Devices Only Boot Segment Program Flash Code Protection Size X11 = No Boot program Flash segment Boot space is 768 Instruction Words (except interrupt vectors) 110 = Standard security; boot program Flash segment ends at 0x0007FE 010 = High security ...
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... WDTPOST<3:0> FWDT ALTI2C FPOR FPWRT<2:0> FPOR © 2007 Microchip Technology Inc. Description Clock Switching Mode bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled Peripheral Pin Select Configuration ...
Page 178
... The BOR Status bit (RCON<1>) is set to indicate that CAP a BOR has occurred. If the BOR circuit is enabled, it continues to operate while in Sleep or Idle mode and resets the device in case VDD falls below the BOR located in threshold voltage. (1) and V . DDCORE Preliminary © 2007 Microchip Technology Inc. ...
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... SWDTEN FWDTEN (divide by N1) LPRC Clock WINDIS © 2007 Microchip Technology Inc. 18.4.2 SLEEP AND IDLE MODES If the WDT is enabled, it will continue to run during Sleep or Idle modes. When the WDT time-out occurs, the device will wake the device and code execution will continue from where the PWRSAV instruction was executed ...
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... GS = 3840 IW 002BFEh 000000h VS = 256 IW 0001FEh 000200h BS = 768 IW 0007FEh 000800h 001FFEh 002000h GS = 4608 IW 002BFEh 000000h VS = 256 IW 0001FEh 000200h 0007FEh BS = 3840 IW 000800h 001FFEh 002000h GS = 1536 IW 002BFEh 000000h VS = 256 IW 0001FEh 000200h 0007FEh BS = 5376 IW 000800h 001FFEh 002000h 002BFEh © 2007 Microchip Technology Inc. ...
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... Any of the following three pairs of programming clock/ data pins can be used: • PGC1/EMUC1 and PGD1/EMUD1 • PGC2/EMUC2 and PGD2/EMUD2 • PGC3/EMUC3 and PGD3/EMUD3 © 2007 Microchip Technology Inc. 18.8 In-Circuit Debugger ® When MPLAB ICD 2 is selected as a debugger, the in- circuit debugging functionality is enabled ...
Page 182
... PIC24HJ32GP202/204 and PIC24HJ16GP304 NOTES: DS70289A-page 180 Preliminary © 2007 Microchip Technology Inc. ...
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... The file register specified by the value ‘f’ • The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2007 Microchip Technology Inc. Most bit-oriented instructions (including simple rotate/shift instructions) have two operands: • The W register (with or without an address modifier) or file register (specified by the value of ‘ ...
Page 184
... Moreover, double word moves require two cycles. The double word instructions execute in two instruction cycles. Note: For more details on the instruction set, refer to the “dsPIC30F/33F Programmer’s Reference Manual” (DS70157). Description Preliminary © 2007 Microchip Technology Inc. ...
Page 185
... One of 16 source working registers ∈ {W0..W15} Wns WREG W0 (working register used in file register instructions) Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws Source W register ∈ Wso { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } © 2007 Microchip Technology Inc. Description Preliminary DS70289A-page 183 ...
Page 186
... Bit Set Ws Write C bit to Ws<Wb> Write Z bit to Ws<Wb> Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Preliminary © 2007 Microchip Technology Inc Status Flags Words Cycles Affected 1 1 C,DC,N,OV,Z ...
Page 187
... Ws,Wnd 33 FF1R FF1R Ws,Wnd 34 GOTO GOTO Expr GOTO Wn © 2007 Microchip Technology Inc. Description Bit Test f Bit Test Bit Test Bit Test Ws<Wb> Bit Test Ws<Wb> Bit Test then Set f Bit Test then Set Bit Test then Set Call subroutine Call indirect subroutine ...
Page 188
... Pop from Top-of-Stack (TOS) to Wdo Pop from Top-of-Stack (TOS) to W(nd):W( Pop Shadow Registers Push f to Top-of-Stack (TOS) Push Wso to Top-of-Stack (TOS) Push W(ns):W( Top-of-Stack (TOS) Push Shadow Registers Go into Sleep or Idle mode Preliminary © 2007 Microchip Technology Inc Status Flags Words Cycles Affected 1 1 C,DC,N,OV,Z ...
Page 189
... SWAP SWAP.b Wn SWAP Wn 65 TBLRDH TBLRDH Ws,Wd © 2007 Microchip Technology Inc. Description Relative Call Computed Call Repeat Next Instruction lit14 + 1 times Repeat Next Instruction (Wn times Software device Reset Return from interrupt Return with literal in Wn Return from Subroutine f = Rotate Left through Carry f ...
Page 190
... DS70289A-page 188 Description Read Prog<15:0> Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink Frame Pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-extend Ws Preliminary © 2007 Microchip Technology Inc Status Flags Words Cycles Affected 1 2 None 1 2 None ...
Page 191
... Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2007 Microchip Technology Inc. 20.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
Page 192
... MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. Preliminary ® DSCs on an instruction © 2007 Microchip Technology Inc. ...
Page 193
... Microchip Technology Inc. 20.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, ...
Page 194
... IrDA , PowerSmart battery management, SEEVAL evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. Preliminary © 2007 Microchip Technology Inc. ® L security ICs, CAN ® ...
Page 195
... Maximum allowable current is a function of device maximum power dissipation (see Table 21-2). 3: Exceptions are CLKOUT, which is able to sink/source 25 mA, and the V and PGDx pins, which are able to sink/source 12 mA. © 2007 Microchip Technology Inc. .................................................................................. -0.3V to +5.6V SS ................................................................................................ 2.25V to 2.75V ...
Page 196
... Max MIPS PIC24HJ32GP202/204 and PIC24HJ16GP304 40 40 Typ Max Unit — +125 °C — +85 °C — +140 °C — +125 ° INT – T )/θ Max Unit Notes — °C — °C/W 1 — °C/W 1 — °C — °C/W 1 © 2007 Microchip Technology Inc. ...
Page 197
... Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 2: This is the limit to which These parameters are characterized but not tested in manufacturing. © 2007 Microchip Technology Inc. Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature (1) Min Typ Max 3.0 — ...
Page 198
... OSC1 DD Preliminary 3.3V 10 MIPS 3.3V 16 MIPS 3.3V 20 MIPS 3.3V 30 MIPS 3.3V 40 MIPS 3.3V 35 MIPS . SS © 2007 Microchip Technology Inc. ...
Page 199
... Base I current is measured with core off, clock on and all modules turned off. Peripheral Module IDLE Disable SFR registers are zeroed. All I/O pins are configured as inputs and pulled to V © 2007 Microchip Technology Inc. ) IDLE Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40° ...
Page 200
... Preliminary ) (3,4) Base Power-Down Current (3) Watchdog Timer Current: ΔI WDT ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions 3.3V 40 MIPS 3.3V 40 MIPS 3.3V 40 MIPS 3.3V 35 MIPS © 2007 Microchip Technology Inc. ...