PIC18LF45J50-I/ML Microchip Technology, PIC18LF45J50-I/ML Datasheet - Page 5
![IC PIC MCU FLASH 32K 2V 44-QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18LF45J50-I/ML
Manufacturer Part Number
PIC18LF45J50-I/ML
Description
IC PIC MCU FLASH 32K 2V 44-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18LF24J50-ISS.pdf
(554 pages)
3.PIC18LF24J50-ISS.pdf
(12 pages)
Specifications of PIC18LF45J50-I/ML
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
44-QFN
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
31 KHz
Number Of Programmable I/os
22
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, MA180024, DM183022
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
4. Module: 10-Bit Analog-to-Digital
TABLE 3:
2010 Microchip Technology Inc.
When the A/D conversion clock select bits are set
for F
Linearity Error (EIL) parameter (A03) and Differen-
tial Linearity Error (EDL) parameter (A04) may
exceed data sheet specifications.
Work around
Select one of the alternate AD clock sources
shown in Table 3. The EIL and EDL parameters
are met for the other clocking options.
Affected Silicon Revisions
ADCON1<2:0>
A2
X
ADCS<2:0>
OSC
110
101
100
011
010
001
A4
X
/2 (ADCON1<2:0> = 000), the Integral
Converter (ADC)
ALTERNATE ADC SETTINGS
Clock Setting
F
F
F
F
F
OSC
OSC
OSC
OSC
OSC
F
RC
/64
/16
/32
/4
/8
PIC18F46J50 FAMILY
5. Module: Parallel Master Port (PMP)
When
(PMMODEH<1:0> = 0x and PMPEN = 1), the data
bus (PMD<7:0>) may not work correctly and
incorrect data could be captured into the PMDIN1L
register.
Work around
None.
Affected Silicon Revisions
A2
X
A4
configured
for
Parallel
DS80436C-page 5
Slave
Port