PIC16C62B-04I/SP Microchip Technology, PIC16C62B-04I/SP Datasheet
PIC16C62B-04I/SP
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PIC16C62B-04I/SP Summary of contents
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... Wide operating voltage range: 2.5V to 5.5V • High Sink/Source Current 25/25 mA • Commercial, Industrial and Extended temperature ranges • Low-power consumption: - < 5V, 4 MHz - 22.5 A typical @ 3V, 32 kHz - < typical standby current 1999 Microchip Technology Inc. PIC16C62B/72A Pin Diagram SDIP, SOIC, SSOP, Windowed CERDIP MCLR/V • RA0/AN0 2 RA1/AN1 ...
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... Capture/Compare/PWM modules Serial Communications 8-bit Analog-to-Digital Module DS35008B-page 2 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT RC7 RC6 RC5/SDO RC4/SDI/SDA PIC16C62B MHz POR, BOR (PWRT, OST) 2K 128 7 Ports A,B SSP — Preliminary PIC16C72A MHz POR, BOR (PWRT, OST) 2K 128 8 Ports A,B,C 3 ...
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... Appendix C: Migration from Base-line to Mid-Range Devices .................................................................................. 112 Index ........................................................................................................................................................................... 113 On-Line Support.......................................................................................................................................................... 117 Reader Response ....................................................................................................................................................... 118 PIC16C62B/72A Product Identification System .......................................................................................................... 119 Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. ...
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... PIC16C62B/72A NOTES: DS35008B-page 4 Preliminary 1999 Microchip Technology Inc. ...
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... Timer0 Timer1 Synchronous CCP1 Serial Port Note 1: Higher order bits are from the STATUS register. 2: The A/D module is not available on the PIC16C62B. 1999 Microchip Technology Inc. PIC16C62B/72A ommended reading for a better understanding of the device architecture and operation of the peripheral modules. There are two devices (PIC16C62B, PIC16C72A) cov- ered by this datasheet ...
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... Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 4: The A/D module is not available on the PIC16C62B. DS35008B-page 6 I/O/P ...
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... PICmicro Mid-Range Reference Manual, (DS33023). 2.1 Program Memory Organization The PIC16C62B/72A devices have a 13-bit program counter capable of addressing program memory space. Each device has words of pro- gram memory. Accessing a location above 07FFh will cause a wraparound. The reset vector is at 0000h and the interrupt vector is at 0004h ...
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... ADCON0 20h General Purpose Registers 7Fh Bank 0 Unimplemented data memory locations, read as ’0’. Note 1: Not a physical register. 2: These registers are not implemented on the PIC16C62B, read as ’0’. Preliminary File Address (1) INDF 80h OPTION_REG 81h PCL 82h STATUS 83h FSR ...
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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: A/D not implemented on the PIC16C62B, maintain as ’0’. 4: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset. ...
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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: A/D not implemented on the PIC16C62B, maintain as ’0’. 4: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset. ...
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... For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. 1999 Microchip Technology Inc. PIC16C62B/72A It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the bits from the STATUS register ...
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... PIC16C62B/72A 2.2.2.2 OPTION_REG REGISTER The OPTION_REG register is a readable and writable register, which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assign- able register known as the prescaler), the External INT Interrupt, TMR0 and the weak pull-ups on PORTB. REGISTER 2-2: ...
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... RBIF: RB Port Change Interrupt Flag bit least one of the RB7:RB4 input pins have changed state (clear by reading PORTB None of the RB7:RB4 input pins have changed state 1999 Microchip Technology Inc. PIC16C62B/72A Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON< ...
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... TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: The PIC16C62B does not have an A/D module. This bit location is reserved on these devices. Always maintain this bit clear. DS35008B-page 14 Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt ...
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... TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software TMR1 register did not overflow Note 1: The PIC16C62B does not have an A/D module. This bit location is reserved on these devices. Always maintain this bit clear. 1999 Microchip Technology Inc. PIC16C62B/72A ...
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... PIC16C62B/72A 2.2.2.6 PCON REGISTER The Power Control register (PCON) contains flag bits to allow differentiation between a Power-on Reset (POR), Brown-Out Reset (BOR) and resets from other sources. . REGISTER 2-6: PCON REGISTER (ADDRESS 8Eh) U-0 U-0 U-0 U-0 — — — — bit7 bit 7-2: Unimplemented: Read as ’ ...
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... The tenth push overwrites the second push (and so on). 1999 Microchip Technology Inc. PIC16C62B/72A 2.4 Program Memory Paging The CALL and GOTO instructions provide 11 bits of address to allow branching within any 2K program memory page ...
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... EXAMPLE 2-1: movlw movwf NEXT clrf incf btfss goto CONTINUE : An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 2-3. However, IRP is not used in the PIC16C62B/72A. 0 IRP (1) bank select 80h 100h 180h not used ...
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... The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. 1999 Microchip Technology Inc. PIC16C62B/72A FIGURE 3-1: Data Bus D ...
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... PIC16C62B only) 85h TRISA — (1) 9Fh ADCON1 — Legend unknown unchanged unimplemented locations read as ’0’. Shaded cells are not used by PORTA. Note 1: The PIC16C62B does not implement the A/D module. Maintain this register clear. DS35008B-page 20 (1) (1) (1) (1) ( REF Bit 5 ...
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... To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>). 1999 Microchip Technology Inc. PIC16C62B/72A Four of PORTB’s pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e. any RB7:RB4 pin con- figured as an output is excluded from the interrupt on change comparison) ...
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... PIC16C62B/72A TABLE 3-3 PORTB FUNCTIONS Name Bit# Buffer (1) RB0/INT bit0 TTL/ST RB1 bit1 TTL RB2 bit2 TTL RB3 bit3 TTL RB4 bit4 TTL RB5 bit5 TTL (2) RB6 bit6 TTL/ST (2) RB7 bit7 TTL/ST Legend: TTL = TTL input Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. ...
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... Schmitt RD TRIS Trigger Peripheral ( PORT Peripheral input Note 1: I/O pins have diode protection Port/Peripheral select signal selects between port data and peripheral output. 3: Peripheral OE (output enable) is only activated if peripheral select is active. 1999 Microchip Technology Inc. PIC16C62B/72A I/O (1) pin and Preliminary DS35008B-page 23 ...
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... PIC16C62B/72A TABLE 3-5 PORTC FUNCTIONS Buffer Name Bit# Function Type bit0 RC0/T1OSO/T1CKI ST Input/output port pin or Timer1 oscillator output/Timer1 clock input RC1/T1OSI bit1 ST Input/output port pin or Timer1 oscillator input RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1 output RC3/SCK/SCL bit3 ST RC3 can also be the synchronous serial clock for both SPI and I modes ...
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... Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>). 2: The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram). 1999 Microchip Technology Inc. PIC16C62B/72A Additional information on external clock requirements is available in the Electrical Specifications section of this manual, and in the PICmicro™ Mid-Range Refer- ence Manual, (DS33023) ...
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... PIC16C62B/72A 4.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software con- trol, (i.e., it can be changed “on-the-fly” during program execution). Note: To avoid an unintended device RESET, a specific instruction sequence (shown in the PICmicro™ Mid-Range Reference Man- ual, DS33023) must be executed when changing the prescaler assignment from Timer0 to the WDT ...
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... Internal clock (F /4) OSC bit 0: TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 1999 Microchip Technology Inc. PIC16C62B/72A 5.1 Timer1 Operation Timer1 can operate in one of these modes: • timer • synchronous counter • asynchronous counter The operating mode is determined by the clock select bit, TMR1CS (T1CON< ...
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... PIC16C62B/72A FIGURE 5-1: TIMER1 BLOCK DIAGRAM Set flag bit TMR1IF on Overflow TMR1 TMR1H T1OSC RC0/T1OSO/T1CKI RC1/T1OSI Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. DS35008B-page 28 0 TMR1L 1 TMR1ON T1SYNC on/off 1 Prescaler ...
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... Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by the Timer1 module. 1999 Microchip Technology Inc. PIC16C62B/72A 5.3 Timer1 Interrupt The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit TMR1IF (PIR1< ...
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... PIC16C62B/72A NOTES: DS35008B-page 30 Preliminary 1999 Microchip Technology Inc. ...
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... TMR2ON: Timer2 On bit 1 = Timer2 Timer2 is off bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 1999 Microchip Technology Inc. PIC16C62B/72A Additional information on timer modules is available in the PICmicro™ (DS33023). FIGURE 6-1: TIMER2 BLOCK DIAGRAM Sets flag TMR2 bit TMR2IF ...
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... PIC16C62B/72A 6.1 Timer2 Operation The Timer2 output is also used by the CCP module to generate the PWM "On-Time", and the PWM period with a match with PR2. The TMR2 register is readable and writable, and is cleared on any device reset. The input clock (F /4) has a prescale option of 1:1, ...
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... Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 and starts an A/D conversion (if A/D module is enabled)) 11xx = PWM mode 1999 Microchip Technology Inc. PIC16C62B/72A Additional information on the CCP module is available in the PICmicro™ Mid-Range Reference Manual, (DS33023). TABLE 7-1 ...
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... PIC16C62B/72A 7.1 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register, when an event occurs on pin RC2/CCP1. An event is defined as: • every falling edge • every rising edge • every 4th rising edge • every 16th rising edge An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON< ...
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... CCP1X Legend unknown unchanged unimplemented read as ’0’. Shaded cells are not used by Capture and Timer1. 1999 Microchip Technology Inc. PIC16C62B/72A 7.2.1 CCP PIN CONFIGURATION The user must configure the RC2/CCP1 pin as an out- put by clearing the TRISC<2> bit. Note: ...
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... PIC16C62B/72A 7.3 PWM Mode In Pulse Width Modulation (PWM) mode, the CCP1 pin produces 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level ...
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... Capture/Compare/PWM register1 (MSB) 17h CCP1CON — — Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by PWM and Timer2. 1999 Microchip Technology Inc. PIC16C62B/72A 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 0xFF 0xFF 0xFF ...
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... PIC16C62B/72A NOTES: DS35008B-page 38 Preliminary 1999 Microchip Technology Inc. ...
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... To reset or reconfigure SPI mode, clear bit SSPEN, re-initialize the SSPCON reg- 1999 Microchip Technology Inc. PIC16C62B/72A ister, and then set bit SSPEN. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRISC register) appro- priately programmed ...
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... PIC16C62B/72A TABLE 8-1 REGISTERS ASSOCIATED WITH SPI OPERATION Address Name Bit 7 Bit 6 0Bh,8Bh INTCON GIE PEIE — 0Ch PIR1 ADIF — 8Ch PIE1 ADIE 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register 14h SSPCON WCOL SSPOV SSPEN 94h SSPSTAT SMP CKE ...
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... SSP Status Register (SSPSTAT) • Serial Receive/Transmit Buffer (SSPBUF) • SSP Shift Register (SSPSR) - Not accessible • SSP Address Register (SSPADD) 1999 Microchip Technology Inc. PIC16C62B/72A The SSPCON register allows control of the I tion. Four mode selection bits (SSPCON<3:0>) allow one of the following I 2 • ...
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... PIC16C62B/72A 8.3.1.1 ADDRESSING Once the SSP module has been enabled, it waits for a START condition to occur. Following the START condi- tion, 8 bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register ...
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... S SSPIF (PIR1<3>) BF (SSPSTAT<0>) SSPOV (SSPCON<6>) 1999 Microchip Technology Inc. PIC16C62B/72A When the address byte overflow condition exists, then no acknowledge (ACK) pulse is given. An overflow con- dition is defined as either bit BF (SSPSTAT<0>) is set or bit SSPOV (SSPCON<6>) is set. An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1< ...
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... PIC16C62B/72A 8.3.1.3 TRANSMISSION When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit and the CKP will be cleared by hardware, holding SCL low ...
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... Shaded cells are not used by SSP module in SPI mode. 2 Note 1: Maintain these bits clear mode. 1999 Microchip Technology Inc. PIC16C62B/72A 8.3.3 MULTI-MASTER OPERATION In multi-master operation, the interrupt generation on the detection of the START and STOP conditions allows the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a reset or when the SSP module is disabled ...
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... PIC16C62B/72A REGISTER 8-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h) R/W-0 R/W-0 R-0 R-0 SMP CKE D/A P bit7 bit 7: SMP: SPI data input sample phase SPI Master Operation 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time ...
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... C firmware controlled master operation (slave idle) 2 1110 = I C slave mode, 7-bit address with start and stop bit interrupts enabled 2 1111 = I C slave mode, 10-bit address with start and stop bit interrupts enabled 1999 Microchip Technology Inc. PIC16C62B/72A R/W-0 R/W-0 R/W-0 R/W-0 SSPM3 SSPM2 SSPM1 ...
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... PIC16C62B/72A NOTES: DS35008B-page 48 Preliminary 1999 Microchip Technology Inc. ...
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... Unimplemented: Read as '0' bit 0: ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shutoff and consumes no operating current 1999 Microchip Technology Inc. PIC16C62B/72A Additional information on the A/D module is available in the PICmicro™ (DS33023). The A/D module has three registers. These registers are: • ...
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... PIC16C62B/72A REGISTER 9-2:ADCON1 REGISTER (ADDRESS 9Fh) U-0 U-0 U-0 U-0 — — — — bit7 bit 7-3: Unimplemented: Read as '0' bit 2-0: PCFG2:PCFG0: A/D Port Configuration Control bits PCFG2:PCFG0 RA0 A 000 A 001 A 010 A 011 A 100 A 101 D 11x A = Analog input D = Digital I/O ...
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... A/D Converter V REF (Reference voltage) 1999 Microchip Technology Inc. PIC16C62B/72A 1. Configure the A/D module: • Configure analog pins / voltage reference / and digital I/O (ADCON1) • Select A/D input channel (ADCON0) • Select A/D conversion clock (ADCON0) • Turn on A/D module (ADCON0) 2 ...
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... PIC16C62B/72A 9.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (C ) must be allowed HOLD to fully charge to the input channel voltage level. The analog input model is shown in Figure 9-2. The source impedance (R ) and the internal sampling switch (R ...
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... When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for sleep operation only. 5: For extended voltage devices (LC), please refer to Electrical Specifications section. 1999 Microchip Technology Inc. PIC16C62B/72A 9.3 Configuring Analog Port Pins . The The ADCON1 and TRISA registers control the opera- AD tion of the A/D port pins ...
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... PIC16C62B/72A 9.4 A/D Conversions Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. 9.5 Use of the CCP Trigger An A/D conversion can be started by the “special event trigger” of the CCP1 module. This requires that the CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be pro- grammed as 1011 and that the A/D module be enabled (ADON bit is set) ...
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... SPECIAL FEATURES OF THE CPU The PIC16C62B/72A devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protec- tion. These are: • Oscillator Mode Selection • Reset - Power-on Reset (POR) ...
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... PIC16CXXX external components may be required in HS mode, as well as XT mode, to avoid overdriving crystals with low drive level specification. 4: Oscillator performance should be verified when migrating between devices (including PIC16C62A to PIC16C62B and PIC16C72 to PIC16C72A) Preliminary CERAMIC RESONATORS Freq OSC1 OSC2 455 kHz ...
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... OSC2/CLKOUT Fosc/4 Recommended values Rext 100 k Cext > 20pF 1999 Microchip Technology Inc. PIC16C62B/72A 10.3 Reset The PIC16CXXX differentiates between various kinds of reset: • Power-on Reset (POR) • MCLR reset during normal operation • MCLR reset during SLEEP • WDT Reset (during normal operation) • ...
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... PIC16C62B/72A FIGURE 10-5: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR SLEEP WDT WDT Module Time-out Reset V rise DD detect Power-on Reset V DD Brown-out Reset BODEN OST/PWRT OST 10-bit Ripple counter OSC1 (1) PWRT On-chip 10-bit Ripple counter RC OSC Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. ...
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... MCLR from external capacitor C in the event of MCLR/V PP down due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). 1999 Microchip Technology Inc. PIC16C62B/72A 10.5 Power-up Timer (PWRT) The Power-up Timer provides a fixed nominal time-out (T , parameter #33) from the POR. The Power-up PWRT Timer operates on an internal RC oscillator ...
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... PIC16C62B/72A 10.8 Time-out Sequence When a POR reset occurs, the PWRT delay starts (if enabled). When PWRT ends, the OST counts 1024 oscillator cycles (LP, XT, HS modes only). When OST completes, the device comes out of reset. The total time-out will vary based on oscillator configuration and the status of the PWRT ...
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... When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 10-5 for reset value for specific condition any device reset, these pins are configured as inputs. 5: This is the value that will be in the port output latch. 1999 Microchip Technology Inc. PIC16C62B/72A Power-on Reset, MCLR Resets Brown-out Reset WDT Reset ...
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... CCP1IE TMR2IF TMR2IE TMR1IF TMR1IE Note 1: The A/D module is not implemented on the PIC16C62B. DS35008B-page 62 The peripheral interrupt flags are contained in the spe- cial function registers PIR1 and PIR2. The correspond- ing interrupt enable bits are contained in special function registers PIE1 and PIE2, and the peripheral interrupt enable bit is contained in special function reg- ister INTCON ...
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... W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W 1999 Microchip Technology Inc. PIC16C62B/72A 10.11 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key reg- isters during an interrupt, (i.e., W register and STATUS register) ...
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... PIC16C62B/72A 10.12 Watchdog Timer (WDT) The Watchdog Timer is a free running on-chip RC oscil- lator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. The WDT will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction ...
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... Wake-up is 1999 Microchip Technology Inc. PIC16C62B/72A regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device resumes execution at the instruction after the SLEEP instruction. If the GIE bit is ...
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... PIC16C62B/72A FIGURE 10-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT OSC1 CLKOUT(4) INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC PC+1 Instruction Inst(PC) = SLEEP Inst( fetched Instruction SLEEP Inst( executed Note 1: XT oscillator mode assumed 1024T (drawing not to scale) This delay will not be there for RC osc mode. ...
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... NOP. One instruc- tion cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction 1999 Microchip Technology Inc. PIC16C62B/72A execution time conditional test is true or the program counter is changed as a result of an instruc- tion, the instruction execution time ...
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... PIC16C62B/72A TABLE 11-2 PIC16CXXX INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f ANDWF f, d AND W with f CLRF f Clear f CLRW - Clear W COMF f, d Complement f DECF f, d Decrement f DECFSZ f, d Decrement f, Skip if 0 INCF f, d Increment f INCFSZ f, d Increment f, Skip if 0 ...
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... Operation: (W) .AND. (k) (W) Status Affected: Z Description: The contents of W register are AND’ed with the eight bit literal 'k'. The result is placed in the W register 1999 Microchip Technology Inc. PIC16C62B/72A ANDWF AND W with f Syntax: [ label ] ANDWF Operands Operation: (W) .AND. (f) Status Affected: Z Description: AND the W register with register 'f' ...
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... PIC16C62B/72A BTFSS Bit Test f, Skip if Set Syntax: [ label ] BTFSS f,b Operands 127 0 b < 7 Operation: skip if (f<b> Status Affected: None Description: If bit ’b’ in register ’f’ is ’0’, then the next instruction is executed. If bit ’b’ is ’1’, then the next instruction ...
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... If ’d’ the result is placed in the W register. If ’d’ the result is placed back in register ’f’. If the result is 1, the next instruction, is executed. If the result is 0, then a NOP is executed instead making instruction. 1999 Microchip Technology Inc. PIC16C62B/72A GOTO Unconditional Branch Syntax: [ label ] Operands: 0 Operation: k PCLATH< ...
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... PIC16C62B/72A IORLW Inclusive OR Literal with W Syntax: [ label ] IORLW k Operands 255 Operation: (W) .OR. k (W) Status Affected: Z Description: The contents of the W register is OR’ed with the eight bit literal 'k'. The result is placed in the W register IORWF Inclusive OR W with f [ label ] Syntax: IORWF f,d Operands: ...
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... TOS PC Status Affected: None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two cycle instruction. 1999 Microchip Technology Inc. PIC16C62B/72A RLF Rotate Left f through Carry Syntax: [ label ] Operands [0,1] ...
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... PIC16C62B/72A SUBLW Subtract W from Literal Syntax: [ label ] SUBLW k Operands 255 Operation (W) W) Status Affected: C, DC, Z Description: The W register is subtracted (2’s com- plement method) from the eight bit lit- eral 'k'. The result is placed in the W register. SUBWF Subtract W from f Syntax: [ label ] SUBWF f,d ...
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... Customizable tool bar and key mapping • A status bar • On-line help 1999 Microchip Technology Inc. PIC16C62B/72A MPLAB allows you to: • Edit your source files (either assembly or ‘C’) • One touch assemble (or compile) and download to PICmicro tools (automatically updates all project information) • ...
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... PIC16C62B/72A 12.4 MPLINK/MPLIB Linker/Librarian MPLINK is a relocatable linker for MPASM and MPLAB-C17 and MPLAB-C18. It can link relocatable objects from assembly or C source files along with pre- compiled libraries using directives from a linker script. MPLIB is a librarian for pre-compiled code to be used with MPLINK ...
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... PIC17C44. All necessary hardware and software is included to run basic demo programs. The users can program the sample microcontrollers provided with 1999 Microchip Technology Inc. PIC16C62B/72A the PICDEM-1 board PRO MATE II or PICSTART-Plus programmer, and easily test firm- ware. The user can also connect the PICDEM-1 board to the MPLAB-ICE emulator and download the firmware to the emulator for testing ...
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... PIC16C62B/72A 12.16 PICDEM-17 The PICDEM- evaluation board that demon- strates the capabilities of several Microchip microcon- trollers, including PIC17C752, PIC17C762, and PIC17C766. All necessary hardware is included to run basic demo programs, which are sup- plied on a 3.5-inch disk. A programmed sample is included, and the user may erase it and program it with ...
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... PIC16C5X á á á á PIC14000 á á á á á PIC12CXXX Tools Software Emulators 1999 Microchip Technology Inc. PIC16C62B/72A á á á á á á á á á á á á á á á á á á ...
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... PIC16C62B/72A NOTES: DS35008B-page 80 Preliminary 1999 Microchip Technology Inc. ...
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... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 1998 Microchip Technology Inc. PIC16C62B/72A (except V , MCLR, and RA4).......................................... -0. ...
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... PIC16C62B/72A FIGURE 13-1: PIC16C62B/72A-20 VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V 5.0 V 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V FIGURE 13-2: PIC16LC62B/72A AND PIC16C62B/72A/JW VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V 5.0 V 4.5 V 4.0 V PIC16LCXXX-04 3.5 V 3.0 V 2 MHz F = (12.0 MHz/V) (V MAX Note the minimum voltage of the PICmicro DDAPPMIN Fmax is no greater than 10 MHz ...
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... FIGURE 13-3: PIC16C62B/72A-04 VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V 5.0 V 4.5 V 4.0 V 3.5 V 3.0 V 2 MHz 1998 Microchip Technology Inc. PIC16C62B/72A PIC16CXXX-04 Frequency Preliminary DS35008B-page 83 ...
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... PIC16C62B/72A 13.1 DC Characteristics: PIC16C62B/72A-04 (Commercial, Industrial, Extended) PIC16C62B/72A-20 (Commercial, Industrial, Extended) DC CHARACTERISTICS Param Sym Characteristic No. D001 V Supply Voltage DD D001A D002* V RAM Data Retention DR Voltage (Note 1) D003 V V Start Voltage to POR DD ensure internal Power-on Reset signal D004 Rise Rate to VDD DD D004A* ensure internal ...
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... This current should be added to the base measurement This is the voltage where the device enters the Brown-out Reset. When BOR is enabled, the device will perform a brown-out reset when V 1998 Microchip Technology Inc. PIC16C62B/72A Standard Operating Conditions (unless otherwise stated) Operating temperature 0° -40° Min Typ† ...
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... PIC16C62B/72A 13.3 DC Characteristics: PIC16C62B/72A-04 (Commercial, Industrial, Extended) PIC16C62B/72A-20 (Commercial, Industrial, Extended) PIC16LC62B/72A-04 (Commercial, Industrial) DC CHARACTERISTICS Param Sym Characteristic No. Input Low Voltage V I/O ports IL D030 with TTL buffer D030A D031 with Schmitt Trigger buffer D032 MCLR, OSC1 (in RC mode) D033 OSC1 (in XT, HS and LP ...
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... RC mode. 2: The leakage current on the MCLR/V levels represent normal operating conditions. Higher leakage current may be measured at different input volt- ages. 3: Negative current is defined as current sourced by the pin. 1998 Microchip Technology Inc. PIC16C62B/72A Standard Operating Conditions (unless otherwise stated) Operating temperature 0° -40° ...
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... PIC16C62B/72A 13.4 AC (Timing) Characteristics 13.4.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created fol- lowing one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings CCP1 ck CLKOUT SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: ...
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... Standard Operating Conditions (unless otherwise stated) Operating temperature Operating voltage V LC parts operate for commercial/industrial temp’s only. FIGURE 13-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 1 V Pin 1998 Microchip Technology Inc. PIC16C62B/72A 0°C T +70°C for commercial A -40°C T +85°C for industrial A -40° ...
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... PIC16C62B/72A 13.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 13-5: EXTERNAL CLOCK TIMING Q4 OSC1 CLKOUT TABLE 13-2: EXTERNAL CLOCK TIMING REQUIREMENTS Param Sym Characteristic No. 1A Fosc External CLKIN Frequency (Note 1) Oscillator Frequency (Note 1) Tosc External CLKIN Period 1 (Note 1) Oscillator Period (Note Instruction Cycle Time (Note 1) ...
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... Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. ††These parameters are asynchronous events not related to any internal clock edge. Note 1: Measurements are taken in RC Mode where CLKOUT output 1998 Microchip Technology Inc. PIC16C62B/72A ...
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... PIC16C62B/72A FIGURE 13-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING V DD MCLR Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET I/O Pins Note: Refer to Figure 13-4 for load conditions. FIGURE 13-8: BROWN-OUT RESET TIMING V DD ...
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... TCKEZtmr1 Delay from external clock edge to timer increment * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 1998 Microchip Technology Inc. PIC16C62B/72A ...
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... PIC16C62B/72A FIGURE 13-10: CAPTURE/COMPARE/PWM TIMINGS CCP1 (Capture Mode) CCP1 (Compare or PWM Mode) Note: Refer to Figure 13-4 for load conditions. TABLE 13-6: CAPTURE/COMPARE/PWM REQUIREMENTS Param Sym Characteristic No. 50* TccL CCP1 input low No Prescaler time With Prescaler 51* TccH CCP1 input high No Prescaler time ...
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... SCK edge † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Specification 73A is only required if specifications 71A and 72A are used. 1998 Microchip Technology Inc. PIC16C62B/72A MSb ...
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... PIC16C62B/72A FIGURE 13-12: EXAMPLE SPI MASTER MODE TIMING (CKE = SCK (CKP = SCK (CKP = 1) SDO MSb SDI MSb IN 74 Note: Refer to Figure 13-4 for load conditions. TABLE 13-8: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. Symbol Characteristic No. 71 TscH SCK input high time ...
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... TscL2ssH † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Specification 73A is only required if specifications 71A and 72A are used. 1998 Microchip Technology Inc. PIC16C62B/72A MSb BIT6 - - - - - -1 ...
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... PIC16C62B/72A FIGURE 13-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = SCK (CKP = 0) 71 SCK (CKP = 1) MSb SDO SDI SDI MSb IN 74 NOTE: Refer to Figure 13-4 for load conditions. TABLE 13-10: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param. Symbol Characteristic No. 70 TssL2scH SCK or SCK input ...
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... STOP condition SU STO Setup time T : STOP condition 93 HD STO Hold time * These parameters are characterized but not tested. 1998 Microchip Technology Inc. PIC16C62B/72A Min Ty Max Unit p s 100 kHz mode 4700 — — ns 400 kHz mode 600 — — 100 kHz mode 4000 — ...
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... PIC16C62B/72A 2 FIGURE 13-16 BUS DATA TIMING 103 SCL 90 91 SDA In 109 SDA Out Note: Refer to Figure 13-4 for load conditions. 2 TABLE 13-12 BUS DATA REQUIREMENTS Param. Sym Characteristic No. 100* T Clock high time HIGH 101* T Clock low time LOW 102* T SDA and SCL rise ...
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... The power-down current spec includes any such leakage from the A/D module current is from RA3 pin or V REF 3: The A/D conversion result never decreases with an increase in the Input Voltage and has no missing codes. 1998 Microchip Technology Inc. PIC16C62B/72A Min Typ† — — — ...
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... PIC16C62B/72A FIGURE 13-17: A/D CONVERSION TIMING BSF ADCON0, GO 134 (Tosc/2) (1) Q4 132 A/D CLK 7 A/D DATA ADRES ADIF GO SAMPLE Note 1: If the A/D clock source is selected as RC, a time of T allows the SLEEP instruction to be executed. TABLE 13-14: A/D CONVERSION REQUIREMENTS Param ...
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... Graphs and Tables not available at this time. Data is not available at this time but you may reference the PIC16C72 Series Data Sheet (DS39016,) DC and AC char- acteristic section, which contains data similar to what is expected. 1999 Microchip Technology Inc. PIC16C62B/72A is standard deviation, over the whole temperature range. Preliminary DD ...
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... PIC16C62B/72A NOTES: DS35008B-page 104 Preliminary 1999 Microchip Technology Inc. ...
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... For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 1999 Microchip Technology Inc. PIC16C62B/72A Example PIC16C72A-04/SP 9917HAT Example Example PIC16C62B-20/SO 9910/SAA Example PIC16C62B 20I/SS025 9917SBP Preliminary PIC16C72A/JW 9917CAT DS35008B-page 105 ...
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... PIC16C62B/72A 15.2 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width ...
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... Ceramic Pkg. Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Window Width Window Length *Controlling Parameter JEDEC Equivalent: MO-058 Drawing No. C04-080 1999 Microchip Technology Inc. PIC16C62B/72A Units INCHES* MIN NOM MAX MIN ...
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... PIC16C62B/72A 15.4 28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Top Lead Thickness Lead Width Mold Draft Angle Top ...
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... Mold Draft Angle Top Mold Draft Angle Bottom *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-150 Drawing No. C04-073 1999 Microchip Technology Inc. PIC16C62B/72A Units INCHES ...
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... PIC16C62B/72A NOTES: DS35008B-page 110 Preliminary 1999 Microchip Technology Inc. ...
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... CCP module CCP does not reset TMR1 when in special event trigger mode. Timer1 module Writing to TMR1L register can cause over- flow in TMR1H register. 1999 Microchip Technology Inc. PIC16C62B/72A Revision Description PIC16C62A/72 2.5V - 5.5V SSP (4 mode SPI) N/A N/A Preliminary PIC16C62B/72A DS35008B-page 111 ...
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... PIC16C62B/72A APPENDIX C: MIGRATION FROM BASE-LINE TO MID-RANGE DEVICES This section discusses how to migrate from a baseline device (i.e., PIC16C5X mid-range device (i.e., PIC16CXXX). The following are the list of modifications over the PIC16C5X microcontroller family: 1. Instruction word length is increased to 14-bits. This allows larger page sizes both in program ...
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... Absolute Maximum Ratings ............................................... 81 ADCON0 Register ........................................................ 9 ADCS1:ADCS0 Bits ................................................... 49 ADON Bit ................................................................... 49 CHS2:CHS0 Bits ....................................................... 49 GO/DONE Bit ..................................................... 49 ADCON1 Register ................................................10 PCFG2:PCFG0 Bits ................................................... 50 ADRES Register .....................................................9 Architecture PIC16C62B/PIC16C72A Block Diagram ..................... 5 Assembler MPASM Assembler ................................................... 75 B Banking, Data Memory ................................................. 8 Brown-out Reset (BOR) .......................... 55 BOR Enable (BODEN Bit) ......................................... 55 BOR Status (BOR Bit) ............................................... 16 Timing Diagram ......................................................... 92 C Capture (CCP Module) ...
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... PICDEM-1 Low-Cost PICmicro Demo Board .................... PICDEM-2 Low-Cost PIC16CXX Demo Board ................. PICDEM-3 Low-Cost PIC16CXXX Demo Board ............... 77 PICSTART Plus Entry Level Development System ........ PIE1 Register ..............................................................10 ADIE Bit ..................................................................... 14 CCP1IE Bit ................................................................ 14 SSPIE Bit ................................................................... 14 TMR1IE Bit ................................................................ TMR2IE Bit ................................................................ 14 Pinout Descriptions , 63 PIC16C62B/PIC16C72A ............................................. 6 Preliminary 1999 Microchip Technology Inc ...
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... Prescaler, Capture ............................................................. 34 Prescaler, Timer0 .............................................................. 25 Assignment (PSA Bit) ......................................... 12 Block Diagram ........................................................... 26 Rate Select (PS2:PS0 Bits) ................................ 12 Switching Between Timer0 and WDT ........................ 26 Prescaler, Timer1 .............................................................. 28 Select (T1CKPS1:T1CKPS0 Bits)............................... 27 1999 Microchip Technology Inc. PIC16C62B/72A , Prescaler, Timer2 .............................................................. 36 15 Select (T2CKPS1:T2CKPS0 Bits) ............................. 31 PRO MATE II Universal Programmer ............................. 77 Program Counter PCL Register .........................................................9 PCLATH Register ...
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... PIC16C62B/72A SSP .................................................................................... 39 Enable (SSPIE Bit) .................................................... 14 Flag (SSPIF Bit) ......................................................... 15 RA5/SS/AN4 Pin .......................................................... 6 RC3/SCK/SCL Pin ....................................................... 6 RC4/SDI/SDA Pin ........................................................ 6 RC5/SDO Pin ............................................................... 6 SSPADD Register ...................................................... 10 SSPBUF Register ........................................................ 9 SSPCON Register ................................................ 9 SSPSTAT Register ............................................. 10 TMR2 Output for Clock Shift ...................................... 32 Write Collision Detect (WCOL Bit) ............................. 47 SSPCON Register ............................................................. 47 CKP Bit ...................................................................... 47 SSPEN Bit ................................................................. 47 SSPM3:SSPM0 Bits .................................................. 47 SSPOV Bit ...
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... Conferences for products, Development Sys- tems, technical information and more • Listing of seminars and events 1999 Microchip Technology Inc. PIC16C62B/72A Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products ...
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... Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y Device: PIC16C62B/72A Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this data sheet easy to follow? If not, why? 4 ...
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... PIC16C62B/72A PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery refer to the factory or the listed sales office. PART NO. -XX X /XX XXX Pattern: Package: Temperature Range: Frequency Range: Device * JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type (including LC devices) ...
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... Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip ...