PIC18F1320-I/P Microchip Technology, PIC18F1320-I/P Datasheet
PIC18F1320-I/P
Specifications of PIC18F1320-I/P
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PIC18F1320-I/P Summary of contents
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... Flash Microcontroller Programming Specification 1.0 DEVICE OVERVIEW This document includes the programming specifications for the following devices: • PIC18F1220 • PIC18F1320 • PIC18F2220 • PIC18F2320 • PIC18F4220 • PIC18F4320 2.0 PROGRAMMING OVERVIEW These devices can be programmed using the high- voltage In-Circuit Serial Programming method, or the low-voltage ICSP method, both while in the user’ ...
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... PIC18F1X20 20-PIN SSOP RA0/AN0 RA1/AN1/LVDIN RA4/T0CKI MCLR/V /RA5 RA2/AN2/V - REF RA3/AN3/V + REF RB0/AN4/INT0 RB1/AN5/TX/CK/INT1 DS39592F-page RB3/CCP1A/P1A 2 19 RB2/P1B/INT2 3 18 OSC1/CLKI/RA7 4 17 OSC2/CLKO/RA6 RB7/PGD/T1OSI/P1D/KBI3 8 13 RB6/PGC/T1OSO/T13CKI/P1C/KBI2 12 9 RB5/PGM/KBI1 10 11 RB4/AN6/RX/DT/KBI0 RB3/CCP1A/P1A RB2/P1B/INT2 OSC1/CLKI/RA7 OSC2/CLKO/RA6 V / RB7/PGD/T1OSI/P1D/KBI3 RB6/PGC/T1OSO/T13CKI/P1C/KBI2 RB5/PGM/KBI1 RB4/AN6/RX/DT/KBI0 2010 Microchip Technology Inc. ...
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... SS NC RA2/AN2/V - REF FIGURE 2-4: PIC18F2X20 28-PIN SDIP (300 MIL), SOIC MCLR/V RA2/AN2/V REF RA3/AN3/V RA4/T0CKI/C1OUT RA5/AN4/SS/LVDIN/C2OUT OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2* RC2/CCP1 RC3/SCK/SCL * Alternate pinout for CCP2 is enabled by a fuse. 2010 Microchip Technology Inc. PIC18FX220/X320 21 1 OSC1/CLKI/RA7 20 2 OSC2/CLKO/RA6 PIC18F1X20 ...
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... DS39592F-page 4 40 /RE3 RA0/AN0 2 38 RA1/AN1 3 37 -/C 4 VREF REF PIC18F4X20 RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0 RB3/AN9/CCP2* RB2/AN8/INT2 RB1/AN10/INT1 RB0/AN12/INT0 RD7/PSP7/P1D RD6/PSP6/P1C RD5/PSP5/P1B RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 NC RC0/T1OSO/T1CKI OSC2/CLKO/RA6 OSC1/CLKI/RA7 RE2/AN7/CS RE1/AN6/WR RE0/AN5/RD RA5/AN4/SS/LVDIN/C2OUT RA4/T0CKI/C1OUT 2010 Microchip Technology Inc. ...
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... The ID locations read out normally, even after code protection is applied. TABLE 2-2: IMPLEMENTATION OF CODE MEMORY Device Code Memory Size (Bytes) PIC18F1220 PIC18F2220 PIC18F4220 PIC18F1320 PIC18F2320 PIC18F4320 FIGURE 2-7: MEMORY MAP FOR PIC18FX220/X320 200000h ID Location 1 200001h ID Location 2 200002h ...
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... TBLPTRL at address 0FF6h DS39592F-page 6 8 Kbytes 0000h Boot Block 200h 07FFh Block 0 0FFFh 17FFh Block 1 1FFFh Unimplemented Unimplemented Read as ‘0’s 200000h 3FFFFFh TBLPTRU TBLPTRH Addr[21:16] Addr[15:8] 2010 Microchip Technology Inc. 4 Kbytes Boot Block Block 0 Block 1 Read as ‘0’s TBLPTRL Addr[7:0] ...
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... EEPROM are written. These memories are then verified to ensure that programming was successful errors are detected, the Configuration bits are then written and verified. FIGURE 2-9: HIGH-LEVEL PROGRAMMING FLOW 2010 Microchip Technology Inc. PIC18FX220/X320 Start Blank Check No Is part Perform Bulk ...
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... TABLE 2-4: SAMPLE COMMAND SEQUENCE 4-Bit Data Core Instruction Command Payload Table Write, 1101 3C 40 post-increment by 2 2010 Microchip Technology Inc. 4-Bit Command 0000 0010 1000 1001 1010 1011 1100 1101 1110 1111 ...
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... The core instruction passes a 16-bit instruction to the CPU core for execution. This is needed to set up registers, as appropriate for use with other commands. If the instruction is a 1-word, 1-cycle instruction, it will be executed while the next command is clocked in. 2010 Microchip Technology Inc. PIC18FX220/X320 (1101 10 11 ...
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... MOVWF TBLPTRH 0000 0E 04 MOVLW 04h 0000 6E F6 MOVWF TBLPTRL 1100 00 80 Write 80h TO 3C0004h to erase entire device. 0000 00 00 NOP 0000 00 00 Hold PGD low until erase completes. 2010 Microchip Technology Inc. Data 80h 81h 83h 88h 89h 8Ah 8Bh ...
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... PGC. After a “Start Programming” com- mand is issued (4-bit command, ‘1111’), a NOP is issued, where the 4th PGC is held high for the duration of the programming time, P9 (see Figure 3-6). 2010 Microchip Technology Inc. PIC18FX220/X320 3.2.1 LOW-VOLTAGE ICSP BULK ERASE ...
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... PIC18FX220/X320 FIGURE 3-4: ERASE AND WRITE BOUNDARIES Panel 1 TBLPTR<21:13> TBLPTR<2:0> TBLPTR<2:0> TBLPTR<2:0> TBLPTR<2:0> TBLPTR<2:0> TBLPTR<2:0> TBLPTR<2:0> TBLPTR<2:0> Offset = TBLPTR<12:3> Note: TBLPTR = TBLPTRU:TBLPTRH:TBLPTRL. DS39592F-page 12 Unimplemented Read as ‘ ’ 0 Erase Region (64 bytes) Offset = TBLPTR<12:6> 2010 Microchip Technology Inc. ...
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... To continue writing data, repeat step 2, where the Address Pointer is incremented each iteration of the loop. FIGURE 3-5: PROGRAM CODE MEMORY FLOW LoopCount = LoopCount + 1 2010 Microchip Technology Inc. PIC18FX220/X320 Core Instruction BSF EECON1, EEPGD BCF EECON1, CFGS MOVLW <Addr[21:16]> ...
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... The erase will begin on the falling edge of the 4th PGC after the WR bit is set. After the erase sequence terminates, PGC must still be held low for the time specified by parameter P10 to allow high-voltage discharge of the memory array. P10 16-Bit Programming Time Data Payload 2010 Microchip Technology Inc. ...
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... To continue writing data, repeat step 7, where the Address Pointer is incremented each iteration of the loop. 2010 Microchip Technology Inc. PIC18FX220/X320 Core Instruction BSF EECON1, EEPGD BCF EECON1, CFGS MOVLW <Addr[21:16]> MOVWF TBLPTRU MOVLW < ...
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... Start Set Address Set Data Enable Write Unlock Sequence 55h – EECON2 0AAh – EECON2 Start Write Sequence Delay P11 + P10 for Write to Occur No Done? Yes Done P11 P11 Data EEPROM 16-Bit Write Time Data Payload 2010 Microchip Technology Inc. ...
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... A6 0000 00 00 0000 00 00 Step 7: Wait for P11 and then disable writes. 0000 94 A6 Repeat steps 2 through 7 to write more data. 2010 Microchip Technology Inc. PIC18FX220/X320 Core Instruction BCF EECON1, EEPGD BCF EECON1, CFGS MOVLW <Addr> MOVWF EEADR MOVLW <Data> ...
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... MOVLW 00h MOVWF TBLPTRH MOVLW 00h MOVWF TBLPTRL Write 2 bytes and post-increment address by 2 Write 2 bytes and post-increment address by 2 Write 2 bytes and post-increment address by 2 Write 2 bytes and start programming NOP - hold PGC high for time P9 2010 Microchip Technology Inc. ...
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... Address Program LSB Delay P9 Time for Write Done 2010 Microchip Technology Inc. PIC18FX220/X320 3.7 Configuration Bits Programming Unlike code memory, the Configuration bits are programmed a byte at a time. The “Table Write, Begin Programming” 4-bit command (1111) is used, but only 8 bits of the following 16-bit payload will be written ...
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... Shift Out Data P14 LSb Shift Data Out PGD = Output READ DATA EEPROM FLOW Start Set Address Read Byte Move to TABLAT Shift Out Data No Done? Yes Done ) 0010 P5A 5 6 MSb Fetch Next 4-Bit Command PGD = Input 2010 Microchip Technology Inc. ...
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... PGD = Input 2010 Microchip Technology Inc. PIC18FX220/X320 P6 must be introduced after the falling edge of the 8th PGC of the operand to allow PGD to transition from an input to an output. During this time, PGC must be held low (see Table 4-2). This operation also increments the Table Pointer by one, pointing to the next byte in code memory for the next read ...
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... Refer to Section 4.1 “Read Data EEPROM Memory” for implementation details of reading data EEPROM. Does No Failure, data? Report Error Yes All ID locations verified? Yes Done 2010 Microchip Technology Inc. ...
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... TABLE 5-1: DEVICE ID VALUE Device PIC18F1220 PIC18F2220 PIC18F4220 PIC18F1320 PIC18F2320 PIC18F4320 2010 Microchip Technology Inc. PIC18FX220/X320 5.3 Single-Supply ICSP Programming The LVP bit in Configuration register, CONFIG4L, enables Single-Supply (Low-Voltage) ICSP Program- ming mode. The LVP bit defaults to a ‘ ...
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... BOR PWRTEN ---- 1111 WDT ---1 1111 — — ---- ---- — — 1--- ---- — STVR 1--- -1-1 — — ---- ---- CP1 CP0 ---- --11 — — 11-- ---- WRT1 WRT0 ---- --11 — — 111- ---- EBTR1 EBTR0 ---- --11 — — -1-- ---- REV1 REV0 Table 5-1 DEV4 DEV3 Table 5-1 2010 Microchip Technology Inc. ...
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... WDT CONFIG2H Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on SWDTEN bit) 2010 Microchip Technology Inc. PIC18FX220/X320 Description set to 2.7V BOR set to 4.2V BOR set to 4.5V BOR DS39592F-page 25 ...
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... Code Protection bit for PIC18F1220 (Block 0 code memory area: 000200h-0007FFh Block 0 is not code-protected 0 = Block 0 is code-protected CP0 CONFIG5L Code Protection bit for PIC18F1320 (Block 0 code memory area: 000200h-000FFFh Block 0 is not code-protected 0 = Block 0 is code-protected Code Protection bit for PIC18F2X20/4X20 CP0 ...
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... Write Protection bit for PIC18F1220 (Block 0 code memory area: 000200h-0007FFh Block 0 is not write-protected 0 = Block 0 is write-protected WRT0 CONFIG6L Write Protection bit for PIC18F1320 (Block 0 code memory area: 000200h-000FFFh Block 0 is not write-protected 0 = Block 0 is write-protected Write Protection bit for PIC18F2X20/4X20 WRT0 ...
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... CONFIG7L (Block 0 code memory area: 000200h-0007FFh Block 0 is not protected from table reads executed in other blocks 0 = Block 0 is protected from table reads executed in other blocks Table Read Protection bit for PIC18F1320 EBTR0 CONFIG7L (Block 0 code memory area: 000200h-000FFFh Block 0 is not protected from table reads executed in other blocks 0 = Block 0 is protected from table reads executed in other blocks Table Read Protection bit for PIC18F2X20/4X20 ...
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... An option to not include the data EEPROM information may be provided. When embed- ding data EEPROM information in the hex file, it should start at address F00000h. Microchip Technology Inc. believes that this feature is important for the benefit of the end customer. 2010 Microchip Technology Inc. PIC18FX220/X320 5 ...
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... PIC18F1320 (CONFIG7H & 040h) + SUM (IDs) Boot/ (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + Panel 1/ ...
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... CONFIG = Sum of locations inclusive SUM[a:b] = Byte-wise sum of lower four bits of all ID locations SUM (IDs) = Addition & = Bit-wise AND 2010 Microchip Technology Inc. PIC18FX220/X320 Checksum 0xAA at 0 Blank and Max Value Address 0F412h 0F368h 0F5E8h 0F59Dh 0FBE7h 0FB9Ch ...
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... Sum of locations inclusive SUM[a:b] = Byte-wise sum of lower four bits of all ID locations SUM (IDs) = Addition & = Bit-wise AND DS39592F-page 32 Checksum 2010 Microchip Technology Inc. 0xAA at 0 Blank and Max Value Address 0E412h 0E368h 0E5E7h 0E59Ch 0EBE6h 0EB9Bh 0F3E4h ...
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... MCLR/V PP Setup Time to MCLR/V P13 Tset2 V DD Data Out Valid from SCK P14 Tvalid PGM Setup Time to MCLR/V P15 Tset3 2010 Microchip Technology Inc. PIC18FX220/X320 Min Max 9.00 13.25 2.00 5.50 2.00 5.50 4.50 5.50 — 300 PP — ...
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... PIC18FX220/X320 NOTES: DS39592F-page 34 2010 Microchip Technology Inc. ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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