PIC18F66J11-I/PT Microchip Technology, PIC18F66J11-I/PT Datasheet - Page 4

• Manufacturer Part Number: PIC18F66J11-I/PT
• Description: IC PIC MCU FLASH 32KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F66J11-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Type: FLASH
• Ram Size: 3930 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 52
• Ram Memory Size: 3.837890625KB
• Cpu Speed: 48MHz
• No. Of Timers: 5
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162091 - HEADER MPLAB ICD2 18F87J11 64/80MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F87J11 FAMILY
4. Module: SRAM
TABLE 3:
DS80495D-page 4
Voltage Regulator Enabled
Temperature = 25°C
SEC_RUN mode using 32 kHz Timer1 Crystal
No RAM access
Typ RAM access
Extreme RAM access
Voltage Regulator Disabled
V
Temperature = 25°C
SEC_RUN mode using 32 kHz Timer1 Crystal
No RAM access
Typ RAM access
Extreme RAM access
Note 1:
DDCORE
Any access to SRAM, either in the form of read
or write operations, will increase the current con-
sumption of the device, depending on how often
the SRAM is accessed. A small current increase
is normal, but in this cited silicon revision, the
difference may be significant and of particular
concern for low-power applications.
For further details, see
Work around
None.
Affected Silicon Revisions
A1
2:
3:
X
Condition
Condition
is tied to V
Code execution patterns where no instructions
access SRAM.
Code execution that accesses SRAM, once
every seven instruction cycles.
Code execution where every instruction cycle
executes an instruction that accesses SRAM.
A2
TYPICAL CURRENT
CONSUMPTION
(1)
(1)
(2)
(2)
A4
DD
(3)
(3)
Case 1:
Case 2:
A5
I
I
Table
DD
DD
201
906
132
723
59
20
(A)
(A)
A6
3.
C1
V
2.5
2.5
2.5
(V)
DD
V
DD
3.3
3.3
3.3
V
(V)
DDCORE
(V)
2.5
2.5
2.5
5. Module: Low-Voltage Detect
6. Module: MSSPx (I
7. Module: Enhanced Universal
The LVDSTAT, V
is not implemented in this revision of silicon.
Work around
None.
Affected Silicon Revisions
If the module is in I
slave performs clock stretching, the first clock
pulse after the slave releases the SCLx line may
be narrower than the configured clock width.
This may result in the slave missing the first
clock in the next transmission/reception.
Work around
If the module is in I
the slave to perform clock stretching. Alter-
nately, the master can slow down the SCLx
clock frequency to a level where the slave can
detect the narrowed clock pulse.
Affected Silicon Revisions
In Synchronous Slave Transmission mode, the
TRMT bit (TXSTA<1>) may not indicate when
the TSR register is empty.
Work around
Instead of polling the TRMT bit to determine the
status of the EUSART, poll the TXIF flag
(PIR1<4>) to determine when new data can be
written to the TXREG register.
Affected Silicon Revisions
A1
A1
A1
X
X
X
A2
A2
A2
X
X
Synchronous Asynchronous
Receiver Transmitter (EUSART)
A4
A4
A4
X
X
DDCORE
2
 2011 Microchip Technology Inc.
C Master mode, do not allow
A5
A5
A5
2
X
X
2
C Master mode, and the
C™ Master)
status bit (WDTCON<6>),
A6
A6
A6
X
X
C1
C1
C1
X
X