PIC24HJ12GP202-I/SO Microchip Technology, PIC24HJ12GP202-I/SO Datasheet - Page 230

• Manufacturer Part Number: PIC24HJ12GP202-I/SO
• Description: IC PIC MCU FLASH 4KX24 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ12GP202-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 12KB (4K x 24)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24HJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit or 10-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164339 - MODULE SKT FOR PM3 28SOICDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24HJ12GP201/202
TABLE 23-1:
DS70282D-page 228
Section 17.0 “10-bit/12-bit
Analog-to-Digital Converter
(ADC)”
Section 18.0 “Special
Features”
Section Name
MAJOR SECTION UPDATES
Updated ADC Conversion Clock Select bits in the AD1CON3 register from
ADCS<5:0> to ADCS<7:0>. Any references to these bits have also been updated
throughout this data sheet (Register 17-3).
Replaced Figure 17-1 (ADC1 Module Block Diagram for PIC24HJ12GP201) and
added Figure 17-2 (ADC1 Block Diagram for PIC24HJ12GP202).
Removed Equation 17-1: ADC Conversion Clock Period and Figure 17-2: ADC
Transfer Function (10-Bit Example).
Added Note 2 to Figure 17-2: ADC Conversion Clock Period Block Diagram.
Updated ADC1 Input Channel 1, 2, 3 Select Register (see Register 17-4) as follows:
• Changed bit 10-9 (CH123NB - PIC24HJ12GP201 devices only) description for
• Updated bit 8 (CH123SB) to reflect device-specific information.
• Updated bit 0 (CH123SA) to reflect device-specific information.
• Changed bit 2-1 (CH123NA - PIC24HJ12GP201 devices only) description for
Updated ADC1 Input Channel 0 Select Register (see Register 17-5) as follows:
• Changed bit value descriptions for bits 12-8
• Changed bit value descriptions for bits 4-0 (PIC24HJ12GP201 devices)
Modified Notes 1 and 2 in the ADC1 Input Scan Select Register Low
(see Register 17-6)
Modified Notes 1 and 2 in the ADC1 Port Configuration Register Low
(see Register 17-7)
Added FICD register information for address 0xF8000E in the Device Configuration
Register Map (see Table 18-1).
Added FICD register content (BKBUG, COE, JTAGEN, and ICS<1:0> to the
PIC24HJ12GP201/202 Configuration Bits Description (see Table 18-2).
Added a note regarding the placement of low-ESR capacitors, after the second
paragraph of Section 18.2 “On-Chip Voltage Regulator” and to Figure 18-1.
Removed the words “if enabled” from the second sentence in the fifth paragraph of
Section 18.3 “BOR: Brown-Out Reset”
bit value of 10 (if AD12B = 0).
bit value of 10 (if AD12B = 0).
Preliminary
Update Description
© 2009 Microchip Technology Inc.