PIC16C716-20I/SO Microchip Technology, PIC16C716-20I/SO Datasheet - Page 66

• Manufacturer Part Number: PIC16C716-20I/SO
• Description: IC MCU OTP 2KX14 A/D PWM 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C716-20I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• For Use With: XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING309-1011 - ADAPTER 18-SOIC TO 18-DIP309-1010 - ADAPTER 18-SOIC TO 18-DIPAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

PIC16C712/716
9.13
Power-Down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (STATUS<3>) is cleared, the
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before the SLEEP instruction was executed (driving
high, low, or high-impedance).
For lowest current consumption in this mode, place all
I/O pins at either V
circuitry is drawing current from the I/O pin, power-
down the A/D and the disable external clocks. Pull all I/
O pins, that are high-impedance inputs, high or low
externally to avoid switching currents caused by float-
ing inputs. The T0CKI input should also be at V
V
from on-chip pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (V
9.13.1
The device can wake up from Sleep through one of the
following events:
1.
2.
3.
External MCLR Reset will cause a device Reset. All
other events are considered a continuation of program
execution and cause a “wake-up”. The TO and PD bits
in the STATUS register can be used to determine the
cause of device Reset. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared if a WDT Time-out occurred (and caused
wake-up).
The following peripheral interrupts can wake the device
from Sleep:
1.
2.
3.
Other peripherals cannot generate interrupts, since
during Sleep, no on-chip clocks are present.
DS41106B-page 64
SS
External Reset input on MCLR pin.
Watchdog Timer Wake-up (if WDT was
enabled).
Interrupt from INT pin, RB port change, or some
peripheral interrupts.
TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
CCP Capture mode interrupt.
Special Event Trigger (Timer1 in Asynchronous
mode using an external clock).
for lowest current consumption. The contribution
Power-down Mode (Sleep)
WAKE-UP FROM SLEEP
DD
or V
SS
, ensure no external
IHMC
DD
).
or
© 2005 Microchip Technology Inc.