PIC16F628-04I/SS Microchip Technology, PIC16F628-04I/SS Datasheet - Page 24
PIC16F628-04I/SS
Manufacturer Part Number
PIC16F628-04I/SS
Description
IC MCU FLASH 2KX14 COMP 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheet
1.PIC16F627-04P.pdf
(170 pages)
Specifications of PIC16F628-04I/SS
Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Core Processor
PIC
Speed
4MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
224 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Controller Family/series
PIC16F
No. Of I/o's
16
Eeprom Memory Size
128Byte
Ram Memory Size
224Byte
Cpu Speed
20MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOPAC164018 - MODULE SKT PROMATEII 20SSOP
Data Converters
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F628-04I/SS
Manufacturer:
MICROCHID
Quantity:
20 000
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PIC16F62X
3.2.2.4
This register contains interrupt enable bits.
REGISTER 3-4:
DS40300C-page 22
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PIE1 Register
PIE1 REGISTER (ADDRESS: 8Ch)
EEIE: EE Write Complete Interrupt Enable Bit
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
CMIE: Comparator Interrupt Enable bit
1 = Enables the comparator interrupt
0 = Disables the comparator interrupt
RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
Unimplemented: Read as ‘0’
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
bit 7
Legend:
R = Readable bit
-n = Value at POR
R/W-0
EEIE
R/W-0
CMIE
R/W-0
RCIE
Preliminary
W = Writable bit
’1’ = Bit is set
R/W-0
TXIE
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
U-0
—
CCP1IE
R/W-0
2003 Microchip Technology Inc.
x = Bit is unknown
TMR2IE
R/W-0
TMR1IE
R/W-0
bit 0
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