PIC24HJ12GP201-I/P Microchip Technology, PIC24HJ12GP201-I/P Datasheet - Page 138

• Manufacturer Part Number: PIC24HJ12GP201-I/P
• Description: IC PIC MCU FLASH 4KX24 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ12GP201-I/P

• Program Memory Type: FLASH
• Program Memory Size: 12KB (4K x 24)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 13
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24HJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit or 6-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164337 - MODULE SOCKET FOR PM3 40DIP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24HJ12GP201/202
15.11 Slope Control
The I
and SCLx signals for Fast mode (400 kHz). The control
bit, DISSLW, enables the user application to disable
slew rate control if desired. It is necessary to disable
the slew rate control for 1 MHz mode.
15.12 Clock Arbitration
Clock arbitration occurs when the master deasserts the
SCLx pin (SCLx allowed to float high) during any
receive, transmit or Restart/Stop condition. When the
SCLx pin is allowed to float high, the BRG is sus-
pended from counting until the SCLx pin is actually
sampled high. When the SCLx pin is sampled high, the
BRG is reloaded with the contents of I2CxBRG and
begins counting. This process ensures that the SCLx
high time will always be at least one BRG rollover count
in the event that the clock is held low by an external
device.
DS70282B-page 136
2
C standard requires slope control on the SDAx
Preliminary
15.13 Multi-Master Communication, Bus
Multi-Master mode support is achieved by bus
arbitration. When the master outputs address/data bits
onto the SDAx pin, arbitration takes place when the
master outputs a ‘1’ on SDAx by letting SDAx float high
while another master asserts a ‘0’. When the SCLx pin
floats high, data should be stable. If the expected data
on SDAx is a ‘1’ and the data sampled on the
SDAx pin = 0, then a bus collision has taken place. The
master will set the I
reset the master portion of the I
15.14 Peripheral Pin Select Limitations
The I
tionality. When the ACTI2C bit in the FPOR configura-
tion register is set to ‘1‘, the module uses the SDAx/
SCLx pins. If the ALTI2C bit is ‘0‘, the module uses the
ASDAx/ASCLx pins.
2
C module has limited peripheral pin select func-
Collision and Bus Arbitration
2
C master events interrupt flag and
© 2007 Microchip Technology Inc.
2
C port to its Idle state.