PIC18LF44J11-I/ML Microchip Technology, PIC18LF44J11-I/ML Datasheet - Page 5
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PIC18LF44J11-I/ML
Manufacturer Part Number
PIC18LF44J11-I/ML
Description
IC PIC MCU FLASH 16K 2V 44-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.MA180023.pdf
(528 pages)
2.PIC18LF24J10-ISS.pdf
(32 pages)
3.PIC18F24J11-ISS.pdf
(14 pages)
4.PIC18F26J11-ISO.pdf
(28 pages)
Specifications of PIC18LF44J11-I/ML
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
44-QFN
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
34
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3776 B
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
31 KHz
Number Of Programmable I/os
22
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180023
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
6. Module: Low-Power Modes (Deep Sleep)
EXAMPLE 2:
7. Module: DC Characteristics (Supply
2010 Microchip Technology Inc.
EnterDeepSleep:
Entering Deep Sleep mode takes approximately
2 T
events that occur during this Deep Sleep entry
period may not generate a wake-up event.
Work around
If using the RTCC alarm for Deep Sleep wake-up,
code should only enter Deep Sleep mode when
the RTCC Value Registers Read Synchronization
bit (RTCCFG<4>) is clear.
This will prevent missing an RTCC alarm that
could occur during the period after the SLEEP
instruction, but before the Deep Sleep mode has
been fully entered.
Affected Silicon Revisions
The minimum operating voltage (V
(D001) for “F” devices is 2.25V. For “LF” devices
(such as the PIC18LF46J11), the minimum rated
V
Work around
None.
Affected Silicon Revisions
bsf
nop
sleep
(…)
goto
DD
A2
A2
X
X
CY
operating voltage is 2.0V.
, following the SLEEP instruction. Wake-up
A4
A4
X
DSCONH, DSEN
EnterDeepSleep
Voltage)
DEEP-SLEEP WAKE-UP WORK AROUND
; Enter Deep Sleep mode on SLEEP instruction
; Not compatible with A2 silicon
; Enter Deep Sleep mode
; Add code here to handle wake up events that may
; have been asserted prior to Deep Sleep entry
; re-attempt Deep Sleep entry if desired
DD
) parameter
PIC18F46J11 FAMILY
8. Module: Special Features (T1DIG)
The A4 revision silicon allows insertion of a
single instruction between setting the Deep
Sleep Enable bit (DSEN, DSCONH<7>) and
issuing the SLEEP instruction (see
The insertion of a NOP instruction before the
SLEEP instruction eliminates the 2 T
where wake-up events could be missed.
Before using this work around, users should
check their device’s revision ID bits to verify that
they have the A4 silicon. This can be done at run
time by a table read from address, 3FFFFEh.
On A2 revision silicon devices, the instruction
cannot be inserted between setting the DSEN
bit and executing the SLEEP instruction, or the
device will enter conventional Sleep mode, not
Deep Sleep.
On A4 silicon devices, if the firmware immedi-
ately executes SLEEP after setting DSEN, the
device will enter Deep Sleep mode without
benefitting from this work around.
The T1DIG Configuration bit (CONFIG2L<3>)
function is not implemented. Effectively, T1DIG is
‘0’ regardless of the value programmed into the bit.
Work around
None.
Affected Silicon Revisions
A2
X
A4
X
DS80435H-page 5
Example
CY
window
2).