PIC16F916-I/SO Microchip Technology, PIC16F916-I/SO Datasheet - Page 205
![IC PIC MCU FLASH 8KX14 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC16F916-I/SO
Manufacturer Part Number
PIC16F916-I/SO
Description
IC PIC MCU FLASH 8KX14 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F913-ISS.pdf
(330 pages)
3.PIC16F913-ISS.pdf
(8 pages)
4.PIC16F913-ISS.pdf
(34 pages)
5.PIC16F913-ISO.pdf
(274 pages)
Specifications of PIC16F916-I/SO
Program Memory Type
FLASH
Program Memory Size
14KB (8K x 14)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
352 B
Interface Type
SSP/I2C/AUSART/SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120
Minimum Operating Temperature
- 40 C
On-chip Adc
5-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F916-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC16F913-ISS PDF datasheet #2
- PIC16F913-ISS PDF datasheet #3
- PIC16F913-ISS PDF datasheet #4
- PIC16F913-ISO PDF datasheet #5
- Current page: 205 of 330
- Download datasheet (7Mb)
14.12.1
Once the SSP module has been enabled, it waits for a
Start condition to occur. Following the Start condition,
the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of register SSPADD <7:1>. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
a)
b)
c)
d)
In 10-bit Address mode, two address bytes need to be
received by the slave (Figure 14-8). The five Most
Significant bits (MSbs) of the first address byte specify
if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must
specify a write so the slave device will receive the
second address byte. For a 10-bit address, the first
byte would equal ‘1111 0 A9 A8 0’, where A9 and
A8 are the two MSbs of the address.
TABLE 14-3:
© 2007 Microchip Technology Inc.
Note:
Transfer is Received
Status Bits as Data
The SSPSR register value is loaded into the
SSPBUF register.
The buffer full bit, BF is set.
An ACK pulse is generated.
SSP interrupt flag bit, SSPIF of the PIR1 register
is set (interrupt is generated if enabled) on the
falling edge of the ninth SCL pulse.
BF
0
1
1
0
ADDRESSING
Shaded cells show the conditions where the user software did not properly clear the overflow condition.
SSPOV
DATA TRANSFER RECEIVED BYTE ACTIONS
0
0
1
1
SSPSR → SSPBUF
Yes
No
No
No
PIC16F913/914/916/917/946
The sequence of events for 10-bit address is as
follows, with steps 7-9 for slave-transmitter:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Generate ACK
Receive first (high) byte of address (bits SSPIF,
BF and bit UA (SSPSTAT<1>) are set).
Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive second (low) byte of address (bits
SSPIF, BF and UA are set).
Update the SSPADD register with the first (high)
byte of address; if match releases SCL line, this
will clear bit UA.
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive repeated Start condition.
Receive first (high) byte of address (bits SSPIF
and BF are set).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Pulse
Yes
No
No
No
(SSP Interrupt occurs
Set bit SSPIF
if enabled)
Yes
Yes
Yes
Yes
DS41250F-page 203
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