PIC18F1220-I/SO Microchip Technology, PIC18F1220-I/SO Datasheet - Page 233

• Manufacturer Part Number: PIC18F1220-I/SO
• Description: IC MCU FLASH 2KX16 A/D 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1220-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 4KB (2K x 16)
• Package / Case: 18-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7-ch x 10-bit
• Package: 18SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA12XP080 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TSTFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2007 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
If CNT
PC
If CNT
PC
Q1
Q1
Q1
No
No
No
register ‘f’
operation
operation
operation
Test f, skip if 0
[ label ] TSTFSZ f [,a]
0 ≤ f ≤ 255
a ∈ [0,1]
skip if f = 0
None
If ‘f’ = 0, the next instruction,
fetched during the current
instruction execution is discarded
and a NOP is executed, making this
a two-cycle instruction. If ‘a’ is ‘0’,
the Access Bank will be selected,
overriding the BSR value. If ‘a’ is
‘1’, then the bank will be selected
as per the BSR value (default).
1
1(2)
Note: 3 cycles if skip and followed
HERE
NZERO
ZERO
Read
0110
Q2
Q2
Q2
No
No
No
=
=
=
≠
=
by a 2-word instruction.
Address (HERE)
0x00,
Address (ZERO)
0x00,
Address (NZERO)
TSTFSZ CNT
:
:
011a
operation
operation
operation
Process
Data
Q3
Q3
Q3
No
No
No
ffff
operation
operation
operation
operation
Q4
Q4
Q4
No
No
No
No
ffff
XORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
W
PIC18F1220/1320
Q1
=
=
literal ‘k’
Exclusive OR literal with W
[ label ] XORLW k
0 ≤ k ≤ 255
(W) .XOR. k → W
N, Z
The contents of W are XOR’ed
with the 8-bit literal ‘k’. The result
is placed in W.
1
1
XORLW 0xAF
Read
Q2
0000
0xB5
0x1A
1010
Process
Data
Q3
DS39605F-page 231
kkkk
Write to W
Q4
kkkk