PIC18LF24J50-I/SP Microchip Technology, PIC18LF24J50-I/SP Datasheet - Page 2

• Manufacturer Part Number: PIC18LF24J50-I/SP
• Description: IC PIC MCU FLASH 16K 2V 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF24J50-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 16
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3776 B
• Interface Type: EUSART/I2C/SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DM183022, MA180024, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F46J50 FAMILY
TABLE 2:
DS80436C-page 2
MSSP
MSSP
EUSART
A/D
PMP
Low-Power
modes
DC
Characteristics
A/D
CTMU
Note 1:
Module
Only those issues indicated in the last column apply to the current silicon revision.
SILICON ISSUE SUMMARY
I
Modes
I
Enable/Dis-
able
F
Clock
PSP
Deep Sleep
Supply Volt-
age
Band Gap
Reference
Constant
Current
2
2
OSC
C™
C Slave
Feature
/2
Number
Item
1.
2.
3.
4.
5.
6.
7.
8.
9.
Must keep LATB<5:4> bits clear.
Module may not receive the correct data if there
is a delay in reading SSPxBUF after SSPxIF
interrupt.
If interrupts are enabled, a 2 T
after re-enabling the module.
F
linearity error limits.
Incorrect data capture in Slave modes.
Wake-up events that occur during Deep Sleep
entry may not generate an event.
Minimum operating voltage (V
“F” devices is 2.25V.
At high V
conversion on Channel 15 could have issues.
Low voltages turn off constant current source.
OSC
/2 A/D Conversion mode may not meet
DD
voltages, performing an A/D
Issue Summary
DD
CY
) parameter for
delay needed
 2010 Microchip Technology Inc.
Revisions
A2
X
X
X
X
X
X
X
X
X
Affected
A4
(1)
X
X
X
X
X