AT90PWM216-16SU Atmel, AT90PWM216-16SU Datasheet - Page 252
AT90PWM216-16SU
Manufacturer Part Number
AT90PWM216-16SU
Description
MCU AVR 16K ISP FLSH 16MHZ24SOIC
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet
1.AT90PWM216-16SU.pdf
(359 pages)
Specifications of AT90PWM216-16SU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
19
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
24-SOIC (7.5mm Width)
Processor Series
AT90PWMx
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Number Of Timers
2
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRFBKIT - KIT DEMO BALLAST FOR AT90PWM2ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK520 - ADAPTER KIT FOR 90PWM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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21.8.4
21.8.4.1
252
AT90PWM216/316
ADC Result Data Registers – ADCH and ADCL
ADLAR = 0
Table 21-6.
1.
.
Table 21-7.
1.
When an ADC conversion is complete, the conversion results are stored in these two result data
registers.
When the ADCL register is read, the two ADC result data registers can’t be updated until the
ADCH register has also been read.
Consequently, in 10-bit configuration, the ADCL register must be read first before the ADCH.
Nevertheless, to work easily with only 8-bit precision, there is the possibility to left adjust the
result thanks to the ADLAR bit in the ADCSRA register. Like this, it is sufficient to only read
ADCH to have the conversion result.
Bit
Read/Write
Initial Value
ADTS3
1
1
1
1
1
1
ADTS3
0
1
1
1
For trigger on any PSC event, if the PSC uses the PLL clock, the core must use PLL/4 clock
source
For trigger on any PSC event, if the PSC uses the PLL clock, the core must use PLL/4 clock
source
ADC Auto Trigger Source Selection for non amplified conversions
ADC Auto Trigger Source Selection for amplified conversions
ADTS2
0
0
1
1
1
1
ADTS2
0
0
0
0
ADC7
R
R
7
0
0
-
ADC6
R
R
6
0
0
-
ADTS1
1
1
0
0
1
1
ADTS1
0
0
0
1
ADC5
R
R
5
0
0
-
ADTS0
0
1
0
1
0
1
ADTS0
0
0
1
0
ADC4
R
R
4
0
0
-
ADC3
R
R
3
0
0
-
Description
PSC2ASY Event
Analog comparator 1
Analog comparator 2
Reserved
Reserved
Reserved
Description
Free Running Mode
PSC0ASY Event
PSC1ASY Event
PSC2ASY Event
ADC2
R
R
2
0
0
-
ADC9
ADC1
R
R
1
0
0
(1)
ADC8
ADC0
R
R
0
0
0
7710E–AVR–08/10
ADCH
ADCL
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