PIC16F648A-I/ML Microchip Technology, PIC16F648A-I/ML Datasheet - Page 3

IC MCU FLASH 4KX14 EEPROM 28QFN

PIC16F648A-I/ML

Manufacturer Part Number
PIC16F648A-I/ML
Description
IC MCU FLASH 4KX14 EEPROM 28QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F648A-I/ML

Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Oscillator Type
Internal
Core Processor
PIC
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Controller Family/series
PIC16F
No. Of I/o's
16
Eeprom Memory Size
256Byte
Ram Memory Size
256Byte
Cpu Speed
20MHz
No.
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT28QFN3 - SOCKET TRAN ICE 18DIP/28QFNI3DBF648 - BOARD DAUGHTER ICEPIC3AC164033 - ADAPTER 28QFN TO 18DIPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
Data Converters
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
4. Module: USART Control
1.
© 2008 Microchip Technology Inc.
USART
RB2/TX/CK differs from the data sheet. Figure
5-9 and Figure 5-10 indicate that the USART
circuit overrides the output drivers via the
Peripheral OE signal. In fact, the Peripheral OE
signal forces the TRISB<2:1> to an output
(Reset) state (see Figure 1). Subsequently, the
TRISB<2:1> must be set or configured to
receive data.
Work around
In Asynchronous mode, when transmit is enabled
(TXEN = 1 and SPEN = 1), the TRISB<2> latch is
cleared to ‘0’ by the USART peripheral circuitry.
When disabling transmit (TXEN = 0), the
TRISB<2> bit should be set to ‘1’ to configure the
RB2/TX/CK pin as an input.
In Synchronous mode, when changing from
transmit to receive, clear the TXEN bit first, then set
TRISB<1> to ‘1’ to configure the RB1/RX/DT pin as
an input before setting SREN or CREN to receive.
When disabling the USART (SPEN = 0), TRIS<2:1>
should be reconfigured for input or output as
required by the application.
control
of
the
RB1/RX/DT
and
PIC16F627A/628A/648A
FIGURE 1:
WR PORTB
WR TRISB
Peripheral OE
RD TRISB
RD PORTB
RBPU
SPEN
USART Output
Data Bus
Note
USART Input
1:
Peripheral OE (output enable) is only active if
peripheral select is active.
(1)
BLOCK DIAGRAM OF RBI, RB2
TRIS Latch
Data Latch
D
D
CK
CK
R
Q
Q
Schmitt
Q
Trigger
Q
Q
EN
1
0
D
TTL
Input
Buffer
DS80151N-page 3
V
P
DD
V
V
Weak
Pull-up
DD
SS

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