PIC18F26K20-E/SP Microchip Technology, PIC18F26K20-E/SP Datasheet - Page 124
![IC PIC MCU FLASH 32KX16 28-DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F26K20-E/SP
Manufacturer Part Number
PIC18F26K20-E/SP
Description
IC PIC MCU FLASH 32KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(456 pages)
3.PIC18F26K20-ISS.pdf
(6 pages)
4.PIC18F26K20-ISS.pdf
(10 pages)
5.PIC18F26K20-ISO.pdf
(430 pages)
Specifications of PIC18F26K20-E/SP
Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
CCP, ECCP, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
64 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC18F25K20T-ISS PDF datasheet
- PIC18F25K20T-ISS PDF datasheet #2
- PIC18F26K20-ISS PDF datasheet #3
- PIC18F26K20-ISS PDF datasheet #4
- PIC18F26K20-ISO PDF datasheet #5
- Current page: 124 of 430
- Download datasheet (7Mb)
PIC18F2XK20/4XK20
10.2
PORTB is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., disable the output driver). Clearing a
TRISB bit (= 0) will make the corresponding PORTB
pin an output (i.e., enable the output driver and put the
contents of the output latch on the selected pin).
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register read and write the latched output value for
PORTB.
EXAMPLE 10-2:
10.3
PORTB pins RB<7:4> have an interrupt-on-change
option. All PORTB pins have a weak pull-up option. An
alternate CCP2 peripheral option is available on RB3.
10.3.1
Each of the PORTB pins has an individually controlled
weak internal pull-up. When set, each bit of the WPUB
register enables the corresponding pin pull-up. When
cleared, the RBPU bit of the INTCON2 register enables
pull-ups on all pins which also have their corresponding
WPUB bit set. When set, the RBPU bit disables all
weak pull-ups. The weak pull-up is automatically turned
off when the port pin is configured as an output. The
pull-ups are disabled on a Power-on Reset.
DS41303D-page 122
CLRF
CLRF
CLRF
MOVLW
MOVWF
Note:
PORTB, TRISB and LATB
Registers
Additional PORTB Pin Functions
PORTB
LATB
ANSELH ; Set RB<4:0> as
0CFh
TRISB
WEAK PULL-UPS
On a Power-on Reset, RB<4:0> are
configured as analog inputs by default and
read as ‘0’; RB<7:5> are configured as
digital inputs.
When the PBADEN Configuration bit is set
to ‘1’, RB<4:0> will alternatively be
configured as digital inputs on POR.
; Initialize PORTB by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; digital I/O pins
;(required if config bit
; PBADEN is set)
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
INITIALIZING PORTB
Preliminary
10.3.2
Four of the PORTB pins (RB<7:4>) are individually
configurable as interrupt-on-change pins. Control bits
in the IOCB register enable (when set) or disable (when
clear) the interrupt function for each pin.
When set, the RBIE bit of the INTCON register enables
interrupts on all pins which also have their correspond-
ing IOCB bit set. When clear, the RBIE bit disables all
interrupt-on-changes.
Only pins configured as inputs can cause this interrupt
to occur (i.e., any RB<7:4> pin configured as an output
is excluded from the interrupt-on-change comparison).
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTB. The ‘mismatch’ outputs of the last read are
OR’d together to set the PORTB Change Interrupt flag
bit (RBIF) in the INTCON register.
This interrupt can wake the device from the Sleep
mode, or any of the Idle modes. The user, in the
Interrupt Service Routine, can clear the interrupt in the
following manner:
a)
b)
A mismatch condition will continue to set the RBIF flag bit.
Reading or writing PORTB will end the mismatch
condition and allow the RBIF bit to be cleared. The latch
holding the last read value is not affected by a MCLR nor
Brown-out Reset. After either one of these Resets, the
RBIF flag will continue to be set if a mismatch is present.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
10.3.3
RB3 can be configured as the alternate peripheral pin
for the CCP2 module by clearing the CCP2MX Config-
uration bit of CONFIG3H. The default state of the
CCP2MX Configuration bit is ‘1’ which selects RC1 as
the CCP2 peripheral pin.
Note:
Any read or write of PORTB to clear the mis-
match condition (except when PORTB is the
source or destination of a MOVFF instruction).
Clear the flag bit, RBIF.
INTERRUPT-ON-CHANGE
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF
interrupt flag may not get set. Furthermore,
since a read or write on a port affects all bits
of that port, care must be taken when using
multiple pins in Interrupt-on-change mode.
Changes on one pin may not be seen while
servicing changes on another pin.
ALTERNATE CCP2 OPTION
© 2008 Microchip Technology Inc.
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