PIC18LF25J11-I/SO Microchip Technology, PIC18LF25J11-I/SO Datasheet - Page 134

• Manufacturer Part Number: PIC18LF25J11-I/SO
• Description: IC PIC MCU FLASH 32K 2V 28-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF25J11-I/SO

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: PIC18
• No. Of I/o's: 16
• Ram Memory Size: 3776Byte
• Cpu Speed: 48MHz
• No. Of Timers: 5
• No. Of Pwm: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F46J11 FAMILY
TABLE 9-5:
DS39932C-page 134
RB4/PMA1/
KBI0/RP7
RB5/PMA0/
KBI1/RP8
RB6/KBI2/
PGC/RP9
RB7/KBI3/
PGD/RP10
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
Note 1:
Pin
2:
3:
input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog
inputs by default when PBADEN is set and digital inputs when PBADEN is cleared.
All other pin functions are disabled when ICSP™ or ICD are enabled.
This bit is not available on 28-pin devices.
PORTB I/O SUMMARY (CONTINUED)
Function
PMA1
PMA0
RP10
KBI0
KBI1
KBI2
PGC
KBI3
PGD
RB4
RP7
RB5
RP8
RB6
RP9
RB7
(3)
(3)
Setting
TRIS
0
1
0
1
1
0
0
1
0
1
1
0
0
1
1
x
1
0
0
1
1
x
x
1
0
I/O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
DIG
TTL
DIG
TTL
DIG
DIG
TTL
DIG
TTL
DIG
DIG
TTL
TTL
DIG
DIG
TTL
TTL
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
LATB<4> data output; not affected by analog input.
PORTB<4> data input; weak pull-up when RBPU bit is
cleared. Disabled when analog input enabled.
Parallel Master Port address.
Interrupt-on-change pin.
Remappable peripheral pin 7 input.
Remappable peripheral pin 7 output.
LATB<5> data output.
PORTB<5> data input; weak pull-up when RBPU bit is
cleared.
Parallel Master Port address.
Interrupt-on-change pin.
Remappable peripheral pin 8 input.
Remappable peripheral pin 8 output.
LATB<6> data output.
PORTB<6> data input; weak pull-up when RBPU bit is
cleared.
Interrupt-on-change pin.
Serial execution (ICSP™) clock input for ICSP and ICD
operation.
Remappable peripheral pin 9 input.
Remappable peripheral pin 9 output.
LATB<7> data output.
PORTB<7> data input; weak pull-up when RBPU bit is
cleared.
Interrupt-on-change pin.
Serial execution data output for ICSP and ICD operation.
Serial execution data input for ICSP and ICD operation.
Remappable peripheral pin 10 input.
Remappable peripheral pin 10 output.
(2)
Description
© 2009 Microchip Technology Inc.
(1)
(2)
(2)