PIC18LF14K50-I/SO Microchip Technology, PIC18LF14K50-I/SO Datasheet - Page 255
![IC PIC MCU FLASH 16KB 20-SOIC](/photos/6/64/66480/150-20-soic_sml.jpg)
PIC18LF14K50-I/SO
Manufacturer Part Number
PIC18LF14K50-I/SO
Description
IC PIC MCU FLASH 16KB 20-SOIC
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F13K50-ISS.pdf
(420 pages)
2.PIC18F13K50-ISS.pdf
(40 pages)
3.PIC18F13K50-ISS.pdf
(10 pages)
4.PIC18F13K50-ISS.pdf
(2 pages)
5.PIC18F13K50-ISO.pdf
(414 pages)
Specifications of PIC18LF14K50-I/SO
Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Controller Family/series
PIC18
No. Of I/o's
15
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
48MHz
No. Of Timers
4
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART, I2C, MSSP, SPI, USB
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
18
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF14K50-I/SO
Manufacturer:
MICROCHIP
Quantity:
1 001
- PIC18F13K50-ISS PDF datasheet
- PIC18F13K50-ISS PDF datasheet #2
- PIC18F13K50-ISS PDF datasheet #3
- PIC18F13K50-ISS PDF datasheet #4
- PIC18F13K50-ISO PDF datasheet #5
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- Download datasheet (4Mb)
22.4
The registers in Bank 2 are used specifically for end-
point buffer control in a structure known as the Buffer
Descriptor Table (BDT). This provides a flexible method
for users to construct and control endpoint buffers of
various lengths and configuration.
The BDT is composed of Buffer Descriptors (BD) which
are used to define and control the actual buffers in the
USB RAM space. Each BD, in turn, consists of four reg-
isters, where n represents one of the 32 possible BDs
(range of 0 to 31):
• BDnSTAT: BD Status register
• BDnCNT: BD Byte Count register
• BDnADRL: BD Address Low register
• BDnADRH: BD Address High register
BDs always occur as a four-byte block in the sequence,
BDnSTAT:BDnCNT:BDnADRL:BDnADRH. The address
of BDnSTAT is always an offset of (4n – 1) (in hexa-
decimal) from 200h, with n being the buffer descriptor
number.
Depending on the buffering configuration used
(Section 22.4.4 “Ping-Pong Buffering”), there are up
to 16, 17 or 32 sets of buffer descriptors. At a minimum,
the BDT must be at least 8 bytes long. This is because
the USB specification mandates that every device must
have Endpoint 0 with both input and output for initial
setup. Depending on the endpoint and buffering
configuration, the BDT can be as long as 128 bytes.
Although they can be thought of as Special Function
Registers, the Buffer Descriptor Status and Address
registers are not hardware mapped, as conventional
microcontroller SFRs in Bank 15 are. If the endpoint cor-
responding to a particular BD is not enabled, its registers
are not used. Instead of appearing as unimplemented
addresses, however, they appear as available RAM.
Only when an endpoint is enabled by setting the
UEPn<1> bit does the memory at those addresses
become functional as BD registers. As with any address
in the data memory space, the BD registers have an
indeterminate value on any device Reset.
An example of a BD for a 64-byte buffer, starting at
280h, is shown in Figure 22-5. A particular set of BD
registers is only valid if the corresponding endpoint has
been enabled using the UEPn register. All BD registers
are available in USB RAM. The BD for each endpoint
should be set up prior to enabling the endpoint.
22.4.1
Buffer descriptors not only define the size of an end-
point buffer, but also determine its configuration and
control. Most of the configuration is done with the BD
Status register, BDnSTAT. Each BD has its own unique
and correspondingly numbered BDnSTAT register.
© 200C Microchip Technology Inc.
Buffer Descriptors and the Buffer
Descriptor Table
BD STATUS AND CONFIGURATION
PIC18F1XK50/PIC18LF1XK50
Preliminary
FIGURE 22-5:
Unlike other control registers, the bit configuration for
the BDnSTAT register is context sensitive. There are
two distinct configurations, depending on whether the
microcontroller or the USB module is modifying the BD
and buffer at a particular time. Only three bit definitions
are shared between the two.
22.4.1.1
Because the buffers and their BDs are shared between
the CPU and the USB module, a simple semaphore
mechanism is used to distinguish which is allowed to
update the BD and associated buffers in memory.
This is done by using the UOWN bit (BDnSTAT<7>) as
a semaphore to distinguish which is allowed to update
the BD and associated buffers in memory. UOWN is the
only bit that is shared between the two configurations
of BDnSTAT.
When UOWN is clear, the BD entry is “owned” by the
microcontroller core. When the UOWN bit is set, the BD
entry and the buffer memory are “owned” by the USB
peripheral. The core should not modify the BD or its
corresponding data buffer during this time. Note that
the microcontroller core can still read BDnSTAT while
the SIE owns the buffer and vice versa.
The buffer descriptors have a different meaning based
on the source of the register update. Prior to placing
ownership with the USB peripheral, the user can con-
figure the basic operation of the peripheral through the
BDnSTAT bits. During this time, the byte count and buf-
fer location registers can also be set.
When UOWN is set, the user can no longer depend on
the values that were written to the BDs. From this point,
the SIE updates the BDs as necessary, overwriting the
original BD values. The BDnSTAT register is updated
by the SIE with the token PID and the transfer count,
BDnCNT, is updated.
Note:
Descriptor
Buffer
Buffer
Address
Memory regions not to scale.
200h
201h
202h
203h
280h
2BFh
Buffer Ownership
BD0ADRH
BD0ADRL
USB Data
BD0STAT
Registers
BD0CNT
EXAMPLE OF A BUFFER
DESCRIPTOR
(xxh)
40h
00h
05h
DS41350C-page 253
Contents
Size of Block
Starting
Address
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