PIC16F1939-I/P Microchip Technology, PIC16F1939-I/P Datasheet - Page 30

IC MCU 8BIT FLASH 40-DIP

PIC16F1939-I/P

Manufacturer Part Number
PIC16F1939-I/P
Description
IC MCU 8BIT FLASH 40-DIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr

Specifications of PIC16F1939-I/P

Core Size
8-Bit
Program Memory Size
28KB (16K x 14)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
36
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC16F
Eeprom Memory Size
256Byte
Ram Memory Size
1024Byte
Cpu Speed
32MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
EUSART, MI2C, SPI
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
36
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 14 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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PIC16F193X/LF193X
3.2.2
The Special Function Registers are registers used by
the application to control the desired operation of
peripheral functions in the device. The registers asso-
ciated with the operation of the peripherals are
described in the appropriate peripheral chapter of this
data sheet.
3.2.3
There are up to 80 bytes of GPR in each data memory
bank.
3.2.3.1
The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3.5.2
“Linear Data Memory” for more information.
3.2.4
There are 16 bytes of common RAM accessible from all
banks.
FIGURE 3-4:
DS41364D-page 30
7-bit Bank Offset
SPECIAL FUNCTION REGISTER
GENERAL PURPOSE RAM
COMMON RAM
Linear Access to GPR
0Bh
0Ch
1Fh
6Fh
7Fh
00h
20h
70h
Special Function Registers
BANKED MEMORY
PARTITIONING
General Purpose RAM
(20 bytes maximum)
(80 bytes maximum)
Memory Region
Core Registers
Common RAM
(12 bytes)
(16 bytes)
Preliminary
3.2.5
The memory maps for the device family are as shown
in Table 3-2.
TABLE 3-2:
PIC16LF1933
PIC16LF1934
PIC16LF1936
PIC16LF1937
PIC16LF1938
PIC16LF1939
PIC16F1933
PIC16F1934
PIC16F1936
PIC16F1937
PIC16F1938
PIC16F1939
Device
DEVICE MEMORY MAPS
MEMORY MAP TABLES
Banks
16-23
23-31
16-23
23-31
16-23
23-31
16-23
23-31
16-23
23-31
16-23
23-31
8-15
8-15
8-15
8-15
8-15
8-15
0-7
0-7
0-7
0-7
0-7
0-7
 2009 Microchip Technology Inc.
Table 3-10, Table 3-13
Table 3-10, Table 3-13
Table 3-10, Table 3-13
Table 3-10, Table 3-13
Table 3-10, Table 3-13
Table 3-10, Table 3-13
Table 3-6, Table 3-11
Table 3-6, Table 3-12
Table 3-8, Table 3-11
Table 3-8, Table 3-12
Table 3-4,Table 3-12
Table 3-4,Table 3-11
Table No.
Table 3-3
Table 3-9
Table 3-3
Table 3-9
Table 3-5
Table 3-9
Table 3-5
Table 3-9
Table 3-7
Table 3-9
Table 3-7
Table 3-9

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