PIC16F818-I/SO Microchip Technology, PIC16F818-I/SO Datasheet - Page 80
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PIC16F818-I/SO
Manufacturer Part Number
PIC16F818-I/SO
Description
IC MCU FLASH 1KX14 18-SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(176 pages)
4.PIC16F818-ISO.pdf
(6 pages)
5.PIC16F818-ISO.pdf
(8 pages)
6.PIC16F818-ISO.pdf
(8 pages)
Specifications of PIC16F818-I/SO
Program Memory Type
FLASH
Program Memory Size
1.75KB (1K x 14)
Package / Case
18-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
I2C/SPI/SSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
Minimum Operating Temperature
- 40 C
On-chip Adc
5-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164010 - MODULE SKT PROMATEII DIP/SOIC
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F818-I/SO
Manufacturer:
MICROCHIP
Quantity:
3 290
Part Number:
PIC16F818-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC16F818/819
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the master-
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then
TABLE 10-2:
FIGURE 10-6:
FIGURE 10-7:
DS39598E-page 78
Note 1:
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
Transfer is Received
Status Bits as Data
BF
0
1
1
0
S
S
Shaded cells show the conditions where the user software did not properly clear the overflow condition.
A7 A6 A5 A4 A3 A2 A1
1
SSPOV
2
A7
Receiving Address
Data is
Sampled
DATA TRANSFER RECEIVED BYTE ACTIONS
1
0
0
1
1
3
A6
2
I
I
2
4
2
C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
C™ WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
A5
Receiving Address
5
3
SSPSR
6
A4
4
R/W = 0
7
A3
5
Yes
8
No
No
No
A2
6
ACK
SSPBUF
9
A1
D7
1
7
D6
2
R/W = 1
SSPBUF register is read
8
Receiving Data
D5
3
Cleared in software
9
Generate ACK Pulse
D4
ACK
Bit SSPOV is set because the SSPBUF register is still full
4
responds to SSPIF
SCL held low
while CPU
D3
5
D2
6
Yes
the data transfer is complete. When the ACK is latched
by the slave device, the slave logic is reset (resets
SSPSTAT register) and the slave device then monitors
for another occurrence of the Start bit. If the SDA line
was low (ACK), the transmit data must be loaded into
the SSPBUF register which also loads the SSPSR
register. Then pin RB4/SCK/SCL should be enabled by
setting bit, CKP.
No
No
No
D1
7
D0
8
D7
SSPBUF is written in software
1
ACK
9
D6
2
Cleared in software
D7
Set bit after writing to SSPBUF
(the SSPBUF must be written to
before the CKP bit can be set)
1
D5
3
D6
2
(SSP interrupt occurs if enabled)
D4
D5
4
Receiving Data
3
D4
Transmitting Data
4
D3
5
2004 Microchip Technology Inc.
ACK is not sent
D3
5
D2
Set bit SSPIF
6
D2
6
From SSP Interrupt
Service Routine
D1
7
Yes
Yes
Yes
Yes
D1
7
D0
D0
8
8
ACK
9
ACK
9
transfer
Bus master
terminates
P
P