PIC18F13K50-I/P Microchip Technology, PIC18F13K50-I/P Datasheet - Page 264

• Manufacturer Part Number: PIC18F13K50-I/P
• Description: IC PIC MCU FLASH 4KX16 20-PDIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F13K50-I/P

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 20-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 14
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART/I2C/MSSP/SPI/USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Package: 20PDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164126 - KIT DEVELOPMENT USB W/PICKIT 2DM164127 - KIT DEVELOPMENT USB 18F14/13K50AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F/LF1XK50
TABLE 22-2:
TABLE 22-3:
DS41350E-page 264
Legend:
BDnSTAT
BDnCNT
BDnADRL
BDnADRH
Note 1:
Endpoint
0
1
2
3
4
5
6
7
Name
2:
3:
4:
(1)
(1)
(1)
(1)
(E) = Even transaction buffer, (O) = Odd transaction buffer
For buffer descriptor registers, n may have a value of 0 to 31. For the sake of brevity, all 32 registers are
shown as one generic prototype. All registers have indeterminate Reset values (xxxx xxxx).
Bits 5 through 2 of the BDnSTAT register are used by the SIE to return PID<3:0> values once the register
is turned over to the SIE (UOWN bit is set). Once the registers have been under SIE control, the values
written for DTSEN and BSTALL are no longer valid.
Prior to turning the buffer descriptor over to the SIE (UOWN bit is cleared), bits 5 through 2 of the
BDnSTAT register are used to configure the DTSEN and BSTALL settings.
This bit is ignored unless DTSEN = 1.
(No Ping-Pong)
Out
10
12
14
0
2
4
6
8
Byte Count
Buffer Address Low
Buffer Address High
ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT
BUFFERING MODES
SUMMARY OF USB BUFFER DESCRIPTOR TABLE REGISTERS
Mode 0
UOWN
Bit 7
13
15
11
In
1
3
5
7
9
DTS
Bit 6
(Ping-Pong on EP0 OUT)
0 (E), 1 (O)
(4)
Out
11
13
15
3
5
7
9
Mode 1
PID3
Bit 5
(2)
Preliminary
BDs Assigned to Endpoint
10
12
14
16
In
2
4
6
8
PID2
Bit 4
12 (E), 13 (O)
16 (E), 17 (O)
20 (E), 21 (O)
24 (E), 25 (O)
28 (E), 29 (O)
(2)
0 (E), 1 (O)
4 (E), 5 (O)
8 (E), 9 (O)
(Ping-Pong on all EPs)
Out
DTSEN
PID1
Bit 3
Mode 2
(2)
(3)
10 (E), 11 (O)
14 (E), 15 (O)
18 (E), 19 (O)
22 (E), 23 (O)
26 (E), 27 (O)
30 (E), 31 (O) 26 (E), 27 (O) 28 (E), 29 (O)
2 (E), 3 (O)
6 (E), 7 (O)
In
BSTALL
PID0
Bit 2
 2010 Microchip Technology Inc.
(2)
(3)
(Ping-Pong on all other EPs,
14 (E), 15 (O) 16 (E), 17 (O)
18 (E), 19 (O) 20 (E), 21 (O)
22 (E), 23 (O) 24 (E), 25 (O)
10 (E), 11 (O) 12 (E), 13 (O)
2 (E), 3 (O)
6 (E), 7 (O)
Out
0
Bit 1
BC9
except EP0)
Mode 3
4 (E), 5 (O)
8 (E), 9 (O)
Bit 0
BC8
In
1