PIC18LF14K50-I/SS Microchip Technology, PIC18LF14K50-I/SS Datasheet - Page 407

• Manufacturer Part Number: PIC18LF14K50-I/SS
• Description: IC PIC MCU FLASH 16K 1.8V 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF14K50-I/SS

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP
• Controller Family/series: PIC18
• No. Of I/o's: 15
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART, I2C, MSSP, SPI, USB
• Maximum Clock Frequency: 32 KHz
• Number Of Programmable I/os: 18
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Package: 20SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

RESET ............................................................................. 333
Reset State of Registers .................................................. 278
Resets ...................................................................... 271, 285
RETFIE ............................................................................ 334
RETLW ............................................................................ 334
RETURN .......................................................................... 335
Return Address Stack ........................................................ 26
Return Stack Pointer (STKPTR) ........................................ 27
Revision History ............................................................... 397
RLCF ................................................................................ 335
RLNCF ............................................................................. 336
RRCF ............................................................................... 336
RRNCF ............................................................................ 337
S
SCK .................................................................................. 135
SDI ................................................................................... 135
SDO ................................................................................. 135
SEC_IDLE Mode .............................................................. 234
SEC_RUN Mode .............................................................. 232
© 2009 Microchip Technology Inc.
PIE2 (Peripheral Interrupt Enable 2) .......................... 71
PIR1 (Peripheral Interrupt Request 1) ....................... 68
PIR2 (Peripheral Interrupt Request 2) ....................... 69
PORTA ....................................................................... 81
PORTB ................................................................. 86, 90
PSTRCON (Pulse Steering Control) ........................ 129
PWM1CON (Enhanced PWM Control) .................... 128
RCON (Reset Control) ....................................... 74, 272
RCSTA (Receive Status and Control) ...................... 187
REFCON0 ................................................................ 243
REFCON1 ................................................................ 243
REFCON2 ................................................................ 244
SLRCON (PORT Slew Rate Control) ......................... 96
SRCON0 (SR Latch Control 0) ................................ 238
SRCON1 (SR Latch Control 1) ................................ 239
SSPADD (MSSP Address and Baud Rate,
SSPCON1 (MSSP Control 1, I
SSPCON1 (MSSP Control 1, SPI Mode) ................. 137
SSPCON2 (MSSP Control 2, I
SSPMSK (SSP Mask) .............................................. 154
SSPSTAT (MSSP Status, SPI Mode) .............. 136, 145
STATUS ..................................................................... 41
STKPTR (Stack Pointer) ............................................ 27
T0CON (Timer0 Control) ............................................ 97
T1CON (Timer1 Control) .......................................... 101
T2CON (Timer2 Control) .......................................... 107
T3CON (Timer3 Control) .......................................... 109
TRISA (Tri-State PORTA) .......................................... 81
TRISB (Tri-State PORTB) .................................... 86, 90
TXSTA (Transmit Status and Control) ..................... 186
UCFG (USB Configuration) ...................................... 248
UCON (USB Control) ............................................... 246
UEIE (USB Error Interrupt Enable) .......................... 264
UEIR (USB Error Interrupt Status) ........................... 263
UEPn (USB Endpoint n Control) .............................. 251
UIE (USB Interrupt Enable) ...................................... 262
UIR (USB Interrupt Status) ...................................... 260
USTAT (USB Status) ............................................... 250
WDTCON (Watchdog Timer Control) ...................... 297
WPUA (Weak Pull-up PORTA) .................................. 82
WPUB (Weak Pull-up PORTB) .................................. 87
Brown-out Reset (BOR) ........................................... 285
Oscillator Start-up Timer (OST) ............................... 285
Power-on Reset (POR) ............................................ 285
Power-up Timer (PWRT) ......................................... 285
SPI Mode) ........................................................ 155
2
2
C Mode) ................. 146
C Mode) ................. 147
PIC18F1XK50/PIC18LF1XK50
Preliminary
Serial Clock, SCK ............................................................ 135
Serial Data In (SDI) .......................................................... 135
Serial Data Out (SDO) ..................................................... 135
Serial Peripheral Interface. See SPI Mode.
SETF ............................................................................... 337
Shoot-through Current ..................................................... 127
Single-Supply ICSP Programming.
Slave Select (SS) ............................................................. 135
Slave Select Synchronization .......................................... 141
SLEEP ............................................................................. 338
Sleep Mode ..................................................................... 233
SLRCON Register ............................................................. 96
Software Simulator (MPLAB SIM) ................................... 354
SPBRG ............................................................................ 189
SPBRGH ......................................................................... 189
Special Event Trigger ...................................................... 209
Special Event Trigger. See Compare (ECCP Mode).
Special Features of the CPU ........................................... 285
Special Function Registers ................................................ 35
SPI Mode
SPI Mode (MSSP)
SR Latch .......................................................................... 237
SRCON0 Register ........................................................... 238
SRCON1 Register ........................................................... 239
SS .................................................................................... 135
SSP
SSPADD Register ............................................................ 155
SSPCON1 Register ................................................. 137, 146
SSPCON2 Register ......................................................... 147
SSPMSK Register ........................................................... 154
SSPOV ............................................................................ 167
SSPOV Status Flag ......................................................... 167
SSPSTAT Register .................................................. 136, 145
Stack Full/Underflow Resets .............................................. 28
Standard Instructions ....................................................... 303
STATUS Register .............................................................. 41
STKPTR Register .............................................................. 27
SUBFSR .......................................................................... 349
SUBFWB ......................................................................... 338
SUBLW ............................................................................ 339
SUBULNK ........................................................................ 349
SUBWF ............................................................................ 339
SUBWFB ......................................................................... 340
SWAPF ............................................................................ 340
Map ............................................................................ 36
Typical Master/Slave Connection ............................ 139
Associated Registers ............................................... 143
Bus Mode Compatibility ........................................... 143
Effects of a Reset .................................................... 143
Enabling SPI I/O ...................................................... 139
Master Mode ............................................................ 140
Operation ................................................................. 138
Operation in Power Managed Modes ...................... 143
Serial Clock ............................................................. 135
Serial Data In ........................................................... 135
Serial Data Out ........................................................ 135
Slave Mode .............................................................. 141
Slave Select ............................................................. 135
Slave Select Synchronization .................................. 141
SPI Clock ................................................................. 140
Typical Connection .................................................. 139
Associated Registers ............................................... 239
Typical SPI Master/Slave Connection ..................... 139
R/W Bit ............................................................ 148, 149
DS41350C-page 405