PIC18F44J10-I/P Microchip Technology, PIC18F44J10-I/P Datasheet - Page 27
PIC18F44J10-I/P
Manufacturer Part Number
PIC18F44J10-I/P
Description
IC PIC MCU FLASH 8KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F24J10-ISO.pdf
(368 pages)
3.PIC18F24J10-ISO.pdf
(6 pages)
4.PIC18F24J10-ISO.pdf
(6 pages)
5.PIC18F24J10-ISO.pdf
(12 pages)
6.PIC18LF24J10-ISS.pdf
(32 pages)
7.PIC18F44J10-IPT.pdf
(358 pages)
Specifications of PIC18F44J10-I/P
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPIC/I2C/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
13-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180013 - MODULE PLUG-IN 18F45J10 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164329 - MODULE SKT FOR 40DIP 18F45J10
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F44J10-I/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC18F44J10-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F44J10-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F24J10-ISO PDF datasheet #2
- PIC18F24J10-ISO PDF datasheet #3
- PIC18F24J10-ISO PDF datasheet #4
- PIC18F24J10-ISO PDF datasheet #5
- PIC18LF24J10-ISS PDF datasheet #6
- PIC18F44J10-IPT PDF datasheet #7
- Current page: 27 of 358
- Download datasheet (6Mb)
2.4
A Phase Locked Loop (PLL) circuit is provided as an
option for users who want to use a lower frequency
oscillator circuit, or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals, or users who require higher
clock speeds from an internal oscillator. For these
reasons, the HSPLL and ECPLL modes are available.
The HSPLL and ECPLL modes provide the ability to
selectively run the device at 4 times the external oscil-
lating source to produce frequencies up to 40 MHz.
The PLL is enabled by setting the PLLEN bit in the
OSCTUNE register (Register 2-1).
REGISTER 2-1:
© 2007 Microchip Technology Inc.
PLL Frequency Multiplier
bit 7
bit 6
bit 5-0
OSCTUNE: PLL CONTROL REGISTER
Unimplemented: Read as ‘0’
PLLEN: Frequency Multiplier PLL Enable bit
1 = PLL enabled
0 = PLL disabled
Unimplemented: Read as ‘0’
bit 7
Legend:
R = Readable bit
-n = Value at POR
Note 1: Available only for ECPLL and HSPLL oscillator configurations; otherwise, this bit is
U-0
—
unavailable and read as ‘0’.
PLLEN
R/W-0
(1)
(1)
U-0
Preliminary
—
W = Writable bit
‘1’ = Bit is set
PIC18F45J10 FAMILY
U-0
—
FIGURE 2-4:
OSC2
OSC1
HSPLL or ECPLL (CONFIG2L)
(1)
PLL Enable (OSCTUNE)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
HS or EC
U-0
—
Mode
F
F
÷4
IN
OUT
PLL BLOCK DIAGRAM
U-0
—
Comparator
Loop
Filter
Phase
VCO
x = Bit is unknown
U-0
—
DS39682C-page 25
SYSCLK
U-0
—
bit 0
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