PIC18F14K50-I/SS Microchip Technology, PIC18F14K50-I/SS Datasheet - Page 355
![IC PIC MCU FLASH 8KX16 20-SSOP](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC18F14K50-I/SS
Manufacturer Part Number
PIC18F14K50-I/SS
Description
IC PIC MCU FLASH 8KX16 20-SSOP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F13K50-ISS.pdf
(420 pages)
2.PIC18F13K50-ISS.pdf
(10 pages)
3.PIC18F13K50-ISS.pdf
(2 pages)
4.PIC18F14K50-ISS.pdf
(4 pages)
5.PIC18F14K50-IP.pdf
(422 pages)
Specifications of PIC18F14K50-I/SS
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
20-SSOP
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
14
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
16 bit
Data Ram Size
768 B
Interface Type
EUSART, I2C, MSSP, SPI, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
15
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Package
20SSOP
Device Core
PIC
Family Name
PIC18
Maximum Speed
48 MHz
Operating Supply Voltage
3.3|5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC244023 - PROC EXTENS PAK PIC18F1XK50DV164126 - KIT DEVELOPMENT USB W/PICKIT 2DM164127 - KIT DEVELOPMENT USB 18F14/13K50AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPXLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F14K50-I/SS
Manufacturer:
IR
Quantity:
14 500
Part Number:
PIC18F14K50-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC18F13K50-ISS PDF datasheet
- PIC18F13K50-ISS PDF datasheet #2
- PIC18F13K50-ISS PDF datasheet #3
- PIC18F14K50-ISS PDF datasheet #4
- PIC18F14K50-IP PDF datasheet #5
- Current page: 355 of 422
- Download datasheet (5Mb)
CALLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description
Words:
Cycles:
Example:
2010 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
operation
Decode
PC
PCLATH =
PCLATU =
W
PC
TOS
PCLATH =
PCLATU =
W
Q1
No
=
=
=
=
=
operation
Subroutine Call Using WREG
CALLW
None
(PC + 2) TOS,
(W) PCL,
(PCLATH) PCH,
(PCLATU) PCU
None
First, the return address (PC + 2) is
pushed onto the return stack. Next, the
contents of W are written to PCL; the
existing value is discarded. Then, the
contents of PCLATH and PCLATU are
latched into PCH and PCU,
respectively. The second cycle is
executed as a
new next instruction is fetched.
Unlike
update W, Status or BSR.
1
2
HERE
WREG
Read
0000
Q2
No
address (HERE)
10h
00h
06h
001006h
address (HERE + 2)
10h
00h
06h
CALL
CALLW
0000
PUSH PC to
, there is no option to
operation
NOP
stack
Q3
No
instruction while the
0001
operation
operation
Q4
No
No
0100
Preliminary
MOVSF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
1st word (source)
2nd word (destin.)
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
Decode
FSR2
Contents
of 85h
REG2
FSR2
Contents
of 85h
REG2
Q1
PIC18F/LF1XK50
source addr
No dummy
Determine
operation
Move Indexed to f
MOVSF [z
0 z
0 f
((FSR2) + z
None
The contents of the source register are
moved to destination register ‘f
actual address of the source register is
determined by adding the 7-bit literal
offset ‘z
FSR2. The address of the destination
register is specified by the 12-bit literal
‘f
can be anywhere in the 4096-byte data
space (000h to FFFh).
The MOVSF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
If the resultant source address points to
an indirect addressing register, the
value returned will be 00h.
2
2
MOVSF
d
’ in the second word. Both addresses
read
1110
1111
Q2
No
=
=
=
=
=
=
d
s
4095
127
s
’ in the first word to the value of
80h
33h
11h
80h
33h
33h
[05h], REG2
s
s
1011
ffff
], f
) f
source addr
Determine
operation
d
Q3
No
d
DS41350D-page 355
0zzz
ffff
source reg
register ‘f’
(dest)
Read
Write
d
Q4
ffff
zzzz
’. The
s
d
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