PIC16LF1938-I/ML Microchip Technology, PIC16LF1938-I/ML Datasheet - Page 247

• Manufacturer Part Number: PIC16LF1938-I/ML
• Description: IC MCU 8BIT FLASH 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1938-I/ML

• Core Size: 8-Bit
• Program Memory Size: 28KB (16K x 14)
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16LF
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 1024Byte
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.2.6
In SPI Master mode, module clocks may be operating
at a different speed than when in full power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the MSSP
clock is much faster than the system clock.
In Slave mode, when MSSP interrupts are enabled,
after the master completes sending data, an MSSP
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSP
interrupts should be disabled.
TABLE 23-1:
 2009 Microchip Technology Inc.
ANSELA
APFCON
INTCON
PIE1
PIR1
SSPBUF
SSPCON1
SSPCON3
SSPSTAT
TRISA
TRISC
Legend:
Name
*
— = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
Page provides register information.
SPI OPERATION IN SLEEP MODE
Synchronous Serial Port Receive Buffer/Transmit Register
TMR1GIE
TMR1GIF
ACKTIM
TRISA7
TRISC7
WCOL
Bit 7
SMP
GIE
—
—
SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
CCP3SEL
TRISC6
SSPOV
TRISA6
ADIE
PCIE
Bit 6
PEIE
ADIF
CKE
—
T1GSEL
TMR0IE
TRISC5
SSPEN
TRISA5
ANSA5
RCIE
RCIF
SCIE
Bit 5
D/A
P2BSEL
TRISA4
TRISC4
ANSA4
BOEN
Preliminary
INTE
TXIE
Bit 4
TXIF
CKP
P
SRNQSEL
SSP1IE
SSP1IF
TRISA3
TRISC3
ANSA3
SDAHT
IOCIE
Bit 3
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the mod-
ule will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all 8 bits have been received, the MSSP
interrupt flag bit will be set and if enabled, will wake the
device.
S
PIC16F193X/LF193X
C2OUTSEL
TMR0IF
CCP1IE
CCP1IF
SBCDE
TRISA2
TRISB2
ANSA2
Bit 2
R/W
SSPM<3:0>
TMR2IE
TMR2IF
TRISA1
TRISC1
ANSA1
SSSEL
AHEN
Bit 1
INTF
UA
CCP2SEL
TMR1IE
TMR1IF
TRISC0
TRISA0
ANSA0
DHEN
IOCIF
DS41364D-page 247
Bit 0
BF
Register
on Page
241*
133
130
100
103
285
287
284
132
140
99