PIC18F24K20-I/SP Microchip Technology, PIC18F24K20-I/SP Datasheet - Page 3
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PIC18F24K20-I/SP
Manufacturer Part Number
PIC18F24K20-I/SP
Description
IC PIC MCU FLASH 8KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(12 pages)
3.PIC18F25K20T-ISS.pdf
(14 pages)
4.PIC18F25K20T-ISS.pdf
(456 pages)
5.PIC18F26K20-ISO.pdf
(430 pages)
Specifications of PIC18F24K20-I/SP
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
CCP/ECCP/EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Operating Supply Voltage
3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 10-bit
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
64 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Silicon Errata Issues
1. Module: ECCP
2. Module: ECCP
3. Module: MSSP SPI
© 2009 Microchip Technology Inc.
Note:
Changing the CCP1M<3:0> bits of CCP1CON
may cause the CCPR1H and CCPR1L registers to
capture the value of Timer1.
Work around
Halt Timer1 before changing ECCP mode. Reload
Timer1 with desired value after ECCP is setup and
before Timer1 is restarted.
Affected Silicon Revisions
Changing direction in Full-Bridge mode does not
insert dead time between changing the active
drivers in common legs of the bridge.
Work around
None.
Affected Silicon Revisions
When the SPI clock is configured for Timer2/2
(SSPCON1<3:0> = 0011), the first SPI high time
may be short.
Work around
Option 1: Ensure TMR2 value rolls over to zero
Option 2: Turn Timer2 off and clear TMR2 before
Affected Silicon Revisions
A4
A4
A4
X
X
X
This document summarizes all silicon
errata issues from all specified revisions of
silicon.
A7
A7
A7
X
X
X
writing SSPBUF. Enable TMR2 after
SSPBUF is written.
immediately before writing to SSPBUF.
A9
A9
A9
X
X
X
AB
AB
AB
X
X
X
PIC18F24/25/44/45K20
4. Module: MSSP I
5. Module: ADC
6. Module: MSSP I
7. Module: MSSP I
Slew rate is slower than I
the SLRCON<2> bit is set.
Work around
Clear SLRCON<2> bit when using the I
peripheral.
Affected Silicon Revisions
Offset error is 3 LSb typical, 7 LSb maximum,
including
component (~2 LSb).
Work around
The time dependent error is insignificant when the
time between conversions is less than 100 ms.
When the time since the previous conversion is
greater than 100 ms then take two ADC
conversions and discard the first.
Affected Silicon Revisions
If a new address byte is received while the BF flag
is set, the SSPOV bit is properly set and an ACK is
properly not generated. If only the SSPOV bit is set
(BF flag was cleared) and a matching address is
clocked in, that received byte will be improperly
loaded into the SSPBUF register and an ACK will
be improperly generated.
Work around
None.
Affected Silicon Revisions
I
Work around
Use software to emulate Master mode.
Affected Silicon Revisions
2
A4
A4
A4
C Master mode is not functional (Rev. A4 only).
A4
X
X
X
X
A7
A7
A7
A7
X
X
X
an
A9
A9
A9
A9
X
X
X
acquisition
2
2
2
AB
AB
AB
AB
X
X
X
C™
C
C
2
C specifications when
time
DS80366G-page 3
dependent
2
C