PIC18LF13K22-I/SO Microchip Technology, PIC18LF13K22-I/SO Datasheet
PIC18LF13K22-I/SO
Specifications of PIC18LF13K22-I/SO
Related parts for PIC18LF13K22-I/SO
PIC18LF13K22-I/SO Summary of contents
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... PIC18F1XK22/LF1XK22 © 2009 Microchip Technology Inc. 20-Pin Flash Microcontrollers with nanoWatt XLP Technology Preliminary Data Sheet DS41365C ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Programmable period from 4ms to 131s • Programmable Code Protection • In-Circuit Serial Programming™ (ICSP™) via two pins • In-Circuit Debug via Two Pins © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Extreme Low-Power Management PIC18LF1XK22 with nanoWatt XLP: • Sleep mode • ...
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... PIC18F1XK22/LF1XK22 TABLE 1: DEVICE OVERVIEW Program Memory Device Bytes Words PIC18F13K22 8K 4K PIC18LF13K22 PIC18F14K22 16K 8K PIC18LF14K22 Note 1: One pin is input-only. DS41365C-page 4 Data Memory Data (1) Pins I/O SRAM EEPROM (bytes) (bytes) 256 256 20 18 12-ch 512 256 20 18 12-ch Preliminary Yes Yes © 2009 Microchip Technology Inc. ...
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... Pin Diagrams 20-pin PDIP, SSOP, SOIC (300 MIL) RA5/OSC1/CLKIN/T13CKI RA4/AN3/OSC2/CLKOUT RA3/MCLR/V RC5/CCP1/P1A RC4/C2OUT/P1B/SRNQ RC3/AN7/C12IN3-/P1C/PGM RC6/AN8/SS RC7/AN9/SDO RB7/TX/CK 20-Pin QFN 4x4 RA3/MCLR/V RC5/CCP1/P1A RC4/C2OUT/P1B/SRNQ RC3/AN7/C12IN3-/P1C/PGM RC6/AN8/SS © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 RA1/AN1/C12IN0-/ RA2/AN2/C1OUT/T0CKI/INT2/SRQ PIC18F1XK22 RC0/AN4/C2IN+ LF1XK22 4 12 RC1/AN5/C12IN1- 5 RC2/AN6/C12IN2-/P1D ...
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... PGM — — — — — — — — — — — — — — — — — — — — — — — — — — — © 2009 Microchip Technology Inc. ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Preliminary DS41365C-page 7 ...
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... PIC18F1XK22/LF1XK22 NOTES: DS41365C-page 8 Preliminary © 2009 Microchip Technology Inc. ...
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... Low Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer are minimized. See Section 25.0 “Electrical Specifications” for values. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F1XK22/LF1XK22 family ...
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... Flash program memory: • 8 Kbytes for PIC18F13K22/LF13K22 • 16 Kbytes for PIC18F14K22/LF14K22 2. On-chip 3.2V LDO regulator for PIC18LF13K22 and PIC18LF14K22. All other features for devices in this family are identical. These are summarized in Table 1-1. The pinouts for all devices are listed in Table 1-1 and I/O description are in Table 1-2 ...
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... Operating Frequency Interrupt Sources I/O Ports Timers Enhanced Capture/ Compare/PWM Modules Serial Communications 10-Bit Analog-to-Digital Module Resets (and Delays) Instruction Set Packages © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 PIC18F13K22 PIC18LF13K22 PIC18F14K22 Yes No 8K 4096 256 DC – 64 MHz 30 Ports MSSP, Enhanced USART ...
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... Reference Timer0 Timer1 Timer2 FVR ADC MSSP EUSART CV 10-bit Preliminary PORTA RA0 RA1 RA1 RA3 RA4 RA5 4 Access Bank 12 PORTB RB4 RB5 RB6 RB7 8 PRODL PORTC RC0 8 RC1 RC2 RC3 8 RC4 RC5 RC6 8 RC7 8 Timer3 REF © 2009 Microchip Technology Inc. ...
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... RB4/AN10/SDI/SDA RB4 AN10 SDI SDA RB5/AN11/RX/DT RB5 AN11 RX DT Legend: TTL = TTL compatible input ST = Schmitt Trigger input O = Output XTAL= Crystal Oscillator © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Pin Number Pin Buffer Type Type 19 16 I/O TTL Digital I/O I Analog ADC channel 0 ...
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... Analog ADC channel 9 O CMOS SPI data out — Ground reference for logic and I/O pins — Positive supply for logic and I/O pins CMOS = CMOS compatible input or output I = Input P = Power Preliminary Description 2 C™ mode © 2009 Microchip Technology Inc. ...
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... MHz internal oscillator, CLKOUT function on RA4/OSC2 Additionally, the 4xPLL may be enabled in hardware or software (under certain conditions) for increased oscil- lator speed. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 2.3 System Clock Selection The SCS bits of the OSCCON register select between the following clock sources: • ...
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... MHz 110 4 MHz 101 2 MHz 100 1 MHz 011 500 kHz 010 250 kHz 001 31 kHz 1 000 0 INTSRC Fail-Safe Clock Watchdog Two-Speed Timer Start-up Preliminary IDLEN Sleep Peripherals System Clock CPU Sleep FOSC<3:0> Clock SCS<1:0> Control © 2009 Microchip Technology Inc. ...
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... This mode is best suited for resonators that require a high drive setting. Figure 2-2 and Figure 2-3 show typical circuits for quartz crystal and ceramic resonators, respectively. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 FIGURE 2-2: QUARTZ CRYSTAL ...
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... This oscillator is enabled or disabled by the T1OSCEN bit of the T1CON register. See Section 10.0 “Timer1 Module” for more information. Internal Clock Preliminary , the capacitor C and the EXT EXT of the DD 0 – 250 kHz 4 – 64 MHz © 2009 Microchip Technology Inc. ...
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... MHZ • 1 MHZ (Default after Reset) • 500 kHz • 250 kHz • 31 kHz © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 The HFIOFS bit of the OSCCON register indicates whether the HFINTOSC is stable. Note 1: Selecting 31 kHz from the HFINTOSC oscillator requires IRCF<2:0> = 000 and the INTSRC bit of the OSCTUNE register to be set ...
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... Source selected by the INTSRC bit of the OSCTUNE register, see text. 3: Default output frequency of HFINTOSC on Reset. DS41365C-page 20 R/W-1 R-q R-0 (1) IRCF0 OSTS HFIOFS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 SCS1 SCS0 bit depends on condition x = Bit is unknown © 2009 Microchip Technology Inc. ...
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... HFIOFL: HFINTOSC Frequency Locked bit 1 = HFINTOSC is in lock 0 = HFINTOSC has not yet locked bit 0 LFIOFS: LFINTOSC Frequency Stable bit 1 = LFINTOSC is stable 0 = LFINTOSC is not stable © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 U-0 U-0 R/W-1 — — PRI_SD U = Unimplemented bit, read as ‘0’ ...
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... For more details about the function of the PLLEN bit see Section 2.10 “4x Phase Lock Loop Frequency Multiplier” R/W-0 R/W-0 R/W-0 TUN4 TUN3 TUN2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 TUN1 TUN0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... New Clk Ready IRCF <2:0> Select Old System Clock Note 1: Start-up time includes T OST © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 2.9 Clock Switching The device contains circuitry to prevent clock “glitches” due to a change of the system clock source. To accomplish this, a short pause in the system clock occurs during the clock switch ...
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... The device is running from the oscillator defined by the FOSC bits of the CONFIG1H Configuration register when the OSTS bit is set. The device is running from the internal oscillator when the OSTS bit is clear. Preliminary Oscillator Delay Oscillator Warm-up Delay (T ) WARM 1024 clock cycles 8 Clock Cycles © 2009 Microchip Technology Inc. ...
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... The internal clock source chosen by the FSCM is determined by the IRCF<2:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 2.12.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared by either one of the following: • ...
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... Test Reset Bit 1 Bit 0 Values on page FOSC1 FOSC0 257 INT0IF RABIF 251 SCS1 SCS0 252 HFIOFL LFIOFS 252 TUN1 TUN0 254 — TMR3IP — 254 — TMR3IE — 254 — TMR3IF — 254 TMR1CS TMR1ON 252 © 2009 Microchip Technology Inc. ...
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... PIC18F13K22/ LF13K22 PIC18F14K22/ LF14K22 Read ‘0’ Read ‘0’ © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 3.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-Mbyte Program Memory (PC) space. Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all ‘ ...
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... The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. Return Address Stack <20:0> 11111 11110 11101 TOSL 34h 00011 001A34h 00010 Top-of-Stack 000D58h 00001 00000 Preliminary Stack Pointer STKPTR<4:0> 00010 © 2009 Microchip Technology Inc. ...
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... SP<4:0>: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software POR. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero ...
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... Table Latch (TABLAT) register contains the data that is read from or written to program memory. Data is transferred to or from program memory one byte at a time. Table read and table write operations are discussed further in Section 4.1 “Table Reads and Table Writes”. Preliminary © 2009 Microchip Technology Inc. nn ...
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... Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 3.2.2 INSTRUCTION FLOW/PIPELINING An “ ...
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... RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code Preliminary address embedded into the 0006h is encoded in the program Word Address ↓ 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h © 2009 Microchip Technology Inc. ...
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... SFRs and the lower portion of GPR Bank 0 without using the Bank Select Register (BSR). Section 3.3.2 “Access Bank” provides a detailed description of the Access RAM. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 3.3.1 BANK SELECT REGISTER (BSR) ...
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... Bank 0). The second 160 bytes are Special Function Registers (from Bank 15). When ‘a’ The BSR specifies the Bank used by the instruction. Access Bank 00h Access RAM Low 5Fh 60h Access RAM High (SFRs) FFh © 2009 Microchip Technology Inc. ...
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... Bank 13 FFh 00h = 1110 Bank 14 FFh 00h = 1111 Bank 15 FFh Note 1: SFRs occupying F53h to F5Fh address space are not in the virtual bank. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Data Memory Map 000h Access RAM 05Fh 060h GPR 0FFh 100h GPR 1FFh ...
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... The MOVFF instruction embeds the entire 12-bit address in the instruction. DS41365C-page 36 Data Memory 000h 7 00h Bank 0 1 FFh 100h 00h Bank 1 FFh 200h 00h Bank 2 FFh 300h 00h Bank 3 through Bank 13 FFh E00h 00h Bank 14 FFh F00h 00h Bank 15 FFFh FFh Preliminary (2) From Opcode © 2009 Microchip Technology Inc. ...
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... The mapping of the Access Bank is slightly different when the extended instruction set is enabled (XINST Configuration bit = 1). This is discussed in more detail in Section 3.5.3 “Mapping the Access Bank in Indexed Literal Offset Mode”. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 3.3.3 GENERAL PURPOSE REGISTER FILE PIC18 devices may have banked memory in the GPR area ...
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... F55h — (2) (2) — F54h — (2) (2) — F53h — IOCB IOCA WPUB WPUA SLRCON (2) — (2) — (2) — (2) — (2) — (2) — (2) — (2) — SRCON1 SRCON0 (2) — (2) — (2) — (2) — (2) — (2) — (2) — (2) — © 2009 Microchip Technology Inc. ...
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... The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See Section 21.4 “Brown-out Reset (BOR)”. 2: The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RA3 reads as ‘0’. This bit is read-only. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Bit 4 Bit 3 Bit 2 Top-of-Stack Upper Byte (TOS< ...
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... STRA ---0 0001 253, 129 ABDEN 0100 0-00 253, 186 PDC0 0000 0000 253, 128 PSSBD0 0000 0000 253, 125 xxxx xxxx 253, 109 xxxx xxxx 253, 109 TMR3ON 0-00 0000 253, 109 © 2009 Microchip Technology Inc. ...
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... The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See Section 21.4 “Brown-out Reset (BOR)”. 2: The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RA3 reads as ‘0’. This bit is read-only. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Bit 4 Bit 3 Bit 2 ...
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... Table 23-2 and Table 23-3. Note: The C and DC bits operate as the borrow and digit borrow bits, respectively, in subtraction. R/W-x R/W-x R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-x R/W-x (1) ( bit Bit is unknown (1) © 2009 Microchip Technology Inc. ...
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... Purpose Register File” location in the Access Bank (Section 3.3.2 “Access Bank”) as the data source for the instruction. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 The Access RAM bit ‘a’ determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR (Section 3.3.1 “ ...
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... W nor the FSR is actually changed in the operation. Accessing the other virtual registers changes the value of the FSR register. ADDWF, INDF1, 1 FSR1H:FSR1L Preliminary 000h Bank 0 100h Bank 1 200h Bank 2 300h 0 Bank 3 through Bank 13 E00h Bank 14 F00h Bank 15 FFFh Data Memory © 2009 Microchip Technology Inc. ...
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... The SFR map remains the same. Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect addressing with FSR0 and FSR1 also remain unchanged. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 3.5.1 INDEXED ADDRESSING WITH LITERAL OFFSET ...
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... F00h Bank 15 F60h SFRs FFFh Data Memory BSR 000h 00000000 060h Bank 0 100h 001001da Bank 1 through Bank 14 F00h Bank 15 F60h SFRs FFFh Data Memory Preliminary © 2009 Microchip Technology Inc. 00h 60h Valid range for ‘f’ FFh ffffffff FSR2L ffffffff ...
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... BSR. F00h F60h FFFh © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use direct addressing as before ...
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... PIC18F1XK22/LF1XK22 NOTES: DS41365C-page 48 Preliminary © 2009 Microchip Technology Inc. ...
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... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 4.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
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... Then WR bit is cleared by hardware at the completion of the write operation. Note: The EEIF interrupt flag bit of the PIR2 register is set when the write is complete. The EEIF flag stays set until cleared by firmware. Preliminary Table Latch (8-bit) TABLAT © 2009 Microchip Technology Inc. ...
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... RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 R/W-0 R/W-x R/W-0 ...
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... Figure 4-3 describes the relevant boundaries of TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write Preliminary the Table Pointer register © 2009 Microchip Technology Inc. ...
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... TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. FIGURE 4-4: READS FROM FLASH PROGRAM MEMORY (Even Byte Address) Instruction Register FETCH (IR) © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 TBLPTRH 8 7 (1) TABLE READ – TBLPTR<21:0> The internal program memory is typically organized by words ...
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... TBLPTRL READ_WORD TBLRD*+ MOVF TABLAT, W MOVWF WORD_EVEN TBLRD*+ MOVFW TABLAT, W MOVF WORD_ODD DS41365C-page 54 ; Load TBLPTR with the base ; address of the word ; read into TABLAT and increment ; get data ; read into TABLAT and increment ; get data Preliminary © 2009 Microchip Technology Inc. ...
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... EECON2 MOVLW 0AAh MOVWF EECON2 BSF EECON1, WR BSF INTCON, GIE © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 4.4.1 FLASH PROGRAM MEMORY ERASE SEQUENCE The sequence of events for erasing a block of internal program memory is: 1. Load Table Pointer register with address of block being erased. ...
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... An example of the required code is given in Example 4-3. Note: Before setting the WR bit, the Table Pointer address needs to be within the intended address range of the bytes in the holding registers. Preliminary 8 (1) TBLPTR = xxxxYY Holding Register © 2009 Microchip Technology Inc. ...
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... D’64’/BlockSize MOVWF COUNTER2 WRITE_BYTE_TO_HREGS MOVF POSTINC0, W MOVWF TABLAT TBLWT+* © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 ; number of bytes in erase block ; point to buffer ; Load TBLPTR with the base ; address of the memory block ; read into TABLAT, and inc ; get data ; store data ...
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... EEIF BCLIF — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) Preliminary Reset Bit 1 Bit 0 Values on page WR RD 253 253 INT0IF RABIF 251 TMR3IP — 254 TMR3IE — 254 TMR3IF — 254 251 251 251 251 © 2009 Microchip Technology Inc. ...
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... EECON1 and EECON2. These are the same registers which control access to the program memory and are used in a similar manner for the data EEPROM. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 The EECON1 register (Register 5-1) is the control reg- ister for data and program memory access. Control bit EEPGD determines if the access will be to program or data EEPROM memory ...
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... When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. DS41365C-page 60 R/W-0 R/W-x R/W-0 FREE WRERR WREN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/S-0 R/S bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... BSF EECON1, WR BSF INTCON, GIE BCF EECON1, WREN © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM ...
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... BCLIP — C2IE EEIE BCLIE — C2IF EEIF BCLIF — Preliminary Reset Bit 1 Bit 0 Values on page 253 EEADR9 EEADR8 253 WR RD 253 253 253 INT0IF RABIF 251 TMR3IP — 254 TMR3IE — 254 TMR3IF — 254 © 2009 Microchip Technology Inc. ...
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... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 EXAMPLE 6- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL ...
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... PRODL RES1 Add cross PRODH products ; WREG ; ; ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products ; WREG ; ; ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H © 2009 Microchip Technology Inc. ...
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... All interrupts branch to address 0008h in Compatibility mode. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 7.2 Interrupt Priority The interrupt priority feature is enabled by setting the IPEN bit of the RCON register ...
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... INT2IE INT2IP IPEN IPEN GIEL/PEIE IPEN TMR0IF TMR0IE TMR0IP (1) RABIF RABIE RABIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Preliminary © 2009 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIEH/GIE Interrupt to CPU Vector to Location 0018h GIEH/GIE GIEL/PEIE ...
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... A mismatch condition will continue to set the RABIF bit. Reading PORTA and PORTB will end the mismatch condition and allow the bit to be cleared and RB port change interrupts also require the individual pin IOCA and IOCB enable. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Note: Interrupt flag bits are set when an interrupt ...
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... This feature allows for software polling. DS41365C-page 68 R/W-1 U-0 R/W-1 INTEDG2 — TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 R/W-1 — RABIP bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 R/W-0 R/W-0 U-0 INT2IE INT1IE — ...
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... R-0 R/W-0 R/W-0 TXIF SSPIF CCP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown ...
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... Unimplemented: Read as ‘0’ bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared by software TMR3 register did not overflow bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 R/W-0 R/W-0 U-0 EEIF BCLIF — Unimplemented bit, read as ‘0’ ...
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... TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt DS41365C-page 72 R/W-0 R/W-0 R/W-0 TXIE SSPIE CCP1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Disabled bit 2 Unimplemented: Read as ‘0’ bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 R/W-0 R/W-0 U-0 EEIE BCLIE — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority DS41365C-page 74 R/W-1 R/W-1 R/W-1 TXIP SSPIP CCP1IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Low priority bit 2 Unimplemented: Read as ‘0’ bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 R/W-1 R/W-1 U-0 EEIP BCLIP — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... The actual Reset value of POR is determined by the type of device Reset. See the notes following this register and Section 21.6 “Reset State of Registers” for additional information. 3: See Table 21-3. DS41365C-page 76 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (3) Preliminary R/W-0 R/W-0 (2) POR BOR bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 7.10 TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L regis- ter pair (FFFFh → 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE of the INTCON register ...
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... PIC18F1XK22/LF1XK22 NOTES: DS41365C-page 78 Preliminary © 2009 Microchip Technology Inc. ...
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... Port Note 1: I/O pins have diode protection to V © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 8.1 PORTA, TRISA and LATA Registers PORTA is 5 bits wide. PORTA<5:4,2:0> bits are bidirectional ports and PORTA is an input-only port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i ...
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... Power-on Reset. EXAMPLE 8-1: INITIALIZING PORTA CLRF PORTA ; Initialize PORTA by ; clearing output ; data latches CLRF LATA ; Alternate method ; to clear output ; data latches MOVLW 030h ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<5:4> as output Preliminary © 2009 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘1’ bit 2-0 TRISA<2:0>: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated PORTA pin configured as an output Note 1: TRISA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 R/W-x R-x R/W-x RA4 RA3 RA2 U = Unimplemented bit, read as ‘ ...
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... R/W-0 R/W-0 IOCA4 IOCA3 IOCA2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-x R/W-x LATA1 LATA0 bit Bit is unknown R/W-1 R/W-1 WPUA1 WPUA0 bit Bit is unknown R/W-0 R/W-0 IOCA1 IOCA0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 83
... DIG = Digital level output; TTL = TTL input buffer Schmitt Trigger input buffer; ANA = Analog level input/output Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: RA3 does not have a corresponding TRISA bit. This pin is always an input regardless of mode. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 I/O ...
Page 84
... WPUA4 WPUA2 WPUA3 Preliminary Reset Bit 1 Bit 0 Values on page ANS1 ANS0 254 INT0IF RABIF 251 — RABIP 251 254 IOCA1 IOCA0 LATA1 LATA0 254 RA1 RA0 254 SLRB SLRA 254 TRISA1 TRISA0 254 WPUA1 WPUA0 251 © 2009 Microchip Technology Inc. ...
Page 85
... PORTB is the source or destination of a MOVFF instruction). b) Clear the flag bit, RABIF. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 A mismatch condition will continue to set the RABIF flag bit. Reading or writing PORTB will end the mismatch condition and allow the RABIF bit to be cleared. The latch holding the last read value is not affected by a MCLR nor Brown-out Reset ...
Page 86
... U-0 U-0 LATB4 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit Bit is unknown U-0 U-0 — — bit Bit is unknown U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 87
... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-4 IOCB<7:4>: Interrupt-on-change bits 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 R/W-1 U-0 U-0 WPUB4 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 88
... Asynchronous serial transmit data output (USART module).. O DIG Synchronous serial clock output (USART module Synchronous serial clock input (USART module Don’t care (TRIS bit does not affect port direction or is overridden for this option). Preliminary Description © 2009 Microchip Technology Inc. ...
Page 89
... SSPCON1 WCOL SSPOV TRISB TRISB7 TRISB6 TXSTA CSRC TX9 WPUB WPUB7 WPUB6 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Bit 5 Bit 4 Bit 3 Bit 2 — — ANS11 ANS10 INT0IE RABIE TMR0IF — ...
Page 90
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 R/W-1 TRISC4 TRISC3 TRISC2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-x R/W-x RC1 RC0 bit Bit is unknown R/W-1 R/W-1 TRISC1 TRISC0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 91
... LATC5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 LATC<7:0>: RB<7:0> Port I/O Output Latch Register bits © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 R/W-x R/W-x R/W-x LATC4 LATC3 LATC2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 92
... PORTC<6> data input. I ANA A/D input channel 8. I TTL Slave select input for SSP (MSSP module) O DIG LATC<7> data output PORTC<7> data input. I ANA A/D input channel 9. O DIG SPI data output (MSSP module).. Preliminary Description © 2009 Microchip Technology Inc. ...
Page 93
... D1EN D1LPS SLRCON — — SSPCON1 WCOL SSPOV TRISC TRISC7 TRISC6 T1CON RD16 T1RUN T3CON RD16 — © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Bit 5 Bit 4 Bit 3 Bit 2 ANS5 ANS4 ANS3 ANS2 — — ANS11 ANS10 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 ...
Page 94
... ANSx bit set will still operate as a digital output but the Input mode will be analog. R/W-1 R/W-1 R/W-1 ANS4 ANS3 ANS2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 ANS1 ANS0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 95
... ANS9: RC7 Analog Select Control bit 1 = Digital input buffer of RC7 is disabled 0 = Digital input buffer of RC7 is enabled bit 0 ANS8: RC6 Analog Select Control bit 1 = Digital input buffer of RC6 is disabled 0 = Digital input buffer of RC6 is enabled © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 U-0 R/W-1 R/W-1 — ANS11 ANS10 U = Unimplemented bit, read as ‘ ...
Page 96
... Note 1: The slew rate of RA4 defaults to standard rate when the pin is used as CLKOUT. DS41365C-page 96 U-0 U-0 R/W-1 — — SLRC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary © 2009 Microchip Technology Inc. R/W-1 R/W-1 SLRB SLRA bit Bit is unknown ...
Page 97
... Microchip Technology Inc. PIC18F1XK22/LF1XK22 The T0CON register (Register 9-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. ...
Page 98
... Timer0 is updated with the contents of TMR0H when a write occurs to TMR0L. This allows all 16 bits of Timer0 to be updated at once. ). OSC 0 Sync with Internal Clocks Programmable 1 Prescaler (2 T Delay Preliminary Set TMR0IF TMR0L on Overflow 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
Page 99
... PORTA RA7 RA6 TMR0H Timer0 Register, High Byte TMR0L Timer0 Register, Low Byte TRISA — — T0CON TMR0ON T08BIT Legend: Shaded cells are not used by Timer0. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 0 Sync with Internal TMR0L Clocks Delay 9.3.1 SWITCHING PRESCALER ...
Page 100
... PIC18F1XK22/LF1XK22 NOTES: DS41365C-page 100 Preliminary © 2009 Microchip Technology Inc. ...
Page 101
... OSC bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 A simplified block diagram of the Timer1 module is shown in Figure 10-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 10-2. Timer1 can also be used to provide Real-Time Clock (RTC) functionality to applications with only a minimal addition of external components and code overhead ...
Page 102
... Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. DS41365C-page 102 Timer1 Clock Input On/Off 1 Prescaler F /4 OSC Internal 0 Clock 2 TMR1CS Clear TMR1 TMR1L (CCP Special Event Trigger) Preliminary 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow © 2009 Microchip Technology Inc. ...
Page 103
... Timer1 Oscillator OSC1/T13CKI OSC2 INTOSC Without CLKOUT (1) T1OSCEN T1CKPS<1:0> T1SYNC TMR1ON Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Timer1 Clock Input 1 Prescaler F /4 OSC Internal 0 ...
Page 104
... TMR1CS proper oscillator start-up. 0 FIGURE 10- Note: See the Notes with Table 10-1 for additional information about capacitor selection. Preliminary EXTERNAL COMPONENTS FOR THE TIMER1 LP OSCILLATOR ® PIC MCU OSC1 XTAL 32.768 kHz OSC2 © 2009 Microchip Technology Inc. ...
Page 105
... Event Trigger, the write operation will take precedence. Note: The Special Event Triggers from the CCP2 module will not set the TMR1IF interrupt flag bit of the PIR1 register. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 10.7 Using Timer1 as a Real-Time Clock Adding an external LP oscillator to Timer1 (such as the C2 one described in Section 10.4 “ ...
Page 106
... TXIE SSPIE CCP1IE RCIF TXIF SSPIF CCP1IF TRISA4 — TRISA2 Preliminary Reset Bit 1 Bit 0 Values on page INT0IF RABIF 251 TMR2IP TMR1IP 254 TMR2IE TMR1IE 254 TMR2IF TMR1IF 254 252 252 TRISA1 TRISA0 254 TMR1CS TMR1ON 252 © 2009 Microchip Technology Inc. ...
Page 107
... TMR2ON: Timer2 On bit 1 = Timer2 Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 11.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 4-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by-16 prescale options ...
Page 108
... SSPIP CCP1IP TXIE SSPIE CCP1IE TXIF SSPIF CCP1IF Preliminary Set TMR2IF TMR2 Output (to PWM or MSSP) PR2 8 Reset Bit 1 Bit 0 Values on page INT0IF RABIF 251 TMR2IP TMR1IP 254 TMR2IE TMR1IE 254 TMR2IF TMR1IF 254 252 252 252 © 2009 Microchip Technology Inc. ...
Page 109
... OSC bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 A simplified block diagram of the Timer3 module is shown in Figure 12-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 12-2. The Timer3 module is controlled through the T3CON register (Register 12-1) ...
Page 110
... Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. DS41365C-page 110 Timer1 Clock Input 1 Prescaler F /4 OSC Internal Clock 0 2 TMR3CS Clear TMR3 TMR3L Preliminary 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow © 2009 Microchip Technology Inc. ...
Page 111
... T1OSCEN T3CKPS<1:0> T3SYNC TMR3ON CCP1 Special Event Trigger CCP1 Select from T3CON<3> Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Timer1 Clock Input 1 Prescaler F /4 OSC ...
Page 112
... BCLIF — TRISA5 TRISA4 — TRISA2 T3SYNC Preliminary Reset Bit 1 Bit 0 Values on page INT0IF RABIF 251 TMR3IP — 254 TMR3IE — 254 TMR3IF — 254 253 253 TRISA1 TRISA0 254 TMR1CS TMR1ON 252 TMR3CS TMR3ON 253 © 2009 Microchip Technology Inc. ...
Page 113
... PWM mode; P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 CCP1 is implemented as a standard CCP module with enhanced PWM capabilities. These include: • ...
Page 114
... The assignment of a particular timer to a module is determined by the Timer-to-CCP enable bits in the T3CON register (Register 12-1). The interactions between the two modules are Figure 13-1. In Asynchronous Counter mode, the capture operation will not work reliably. DS41365C-page 114 summarized in Preliminary © 2009 Microchip Technology Inc. ...
Page 115
... FIGURE 13-1: CAPTURE MODE OPERATION BLOCK DIAGRAM CCP1 pin Prescaler ÷ CCP1CON<3:0> Q1:Q4 © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 be used with each CCP module is selected in the T3CON register (see Section 13.1.1 “CCP Module and Timer Resources”). 13.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated ...
Page 116
... The Special Event Trigger can also start an A/D conver- sion. In order to do this, the A/D converter must already be enabled. Special Event Trigger (Timer1/Timer3 Reset, A/D Trigger) Set CCP1IF Compare Output Match Logic 4 CCP1CON<3:0> Preliminary Special Event Trigger mode CCP1 pin TRIS Output Enable © 2009 Microchip Technology Inc. ...
Page 117
... Full-Bridge, Reverse 11 Note 1: Outputs are enabled by pulse steering in Single mode. See Register 13-4. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 The PWM outputs are multiplexed with I/O pins and are designated P1A, P1B, P1C and P1D. The polarity of the PWM pins is configurable and is selected by setting the CCP1M bits in the CCP1CON register appropriately ...
Page 118
... Pulse Width = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (PWM1CON<6:0>) OSC Note 1: Dead-band delay is programmed using the PWM1CON register (Section 13.4.6 “Programmable Dead-Band Delay Mode”). DS41365C-page 118 Pulse 0 Width Period (1) (1) Delay Delay Preliminary © 2009 Microchip Technology Inc. PR2+1 ...
Page 119
... OSC • Pulse Width = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (PWM1CON<6:0>) OSC Note 1: Dead-band delay is programmed using the PWM1CON register (Section 13.4.6 “Programmable Dead-Band Delay Mode”). © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Pulse 0 Width Period (1) (1) Delay Delay ...
Page 120
... Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. FET Driver P1A Load FET Driver P1B V+ FET Driver Load FET Driver Preliminary EXAMPLE OF HALF-BRIDGE PWM OUTPUT Period td (1) ( FET Driver FET Driver © 2009 Microchip Technology Inc. ...
Page 121
... P1A, P1B, P1C and P1D outputs are multiplexed with the PORT data latches. The associated TRIS bits must be cleared to configure the P1A, P1B, P1C and P1D pins as outputs. FIGURE 13-8: EXAMPLE OF FULL-BRIDGE APPLICATION P1A P1B P1C P1D © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 V+ QA FET Driver Load FET Driver QB ...
Page 122
... Forward Mode (2) P1A Pulse Width (2) P1B (2) P1C (2) P1D (1) Reverse Mode Pulse Width (2) P1A (2) P1B (2) P1C (2) P1D (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signal is shown as active-high. DS41365C-page 122 Period (1) Period (1) Preliminary © 2009 Microchip Technology Inc. ...
Page 123
... When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle. The modulated P1B and P1D signals are inactive at this time. The length of this time is (1/F value. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 The Full-Bridge mode does not provide dead-band delay ...
Page 124
... PWM cycle before enabling the PWM pin output drivers. The completion of a full PWM cycle is indicated by the TMR2IF bit of the PIR1 register being set as the second PWM period begins. DS41365C-page 124 Forward Period Reverse Period Preliminary PW OFF – T OFF ON © 2009 Microchip Technology Inc. ...
Page 125
... PSSBDn: Pins P1B and P1D Shutdown State Control bits 00 = Drive pins P1B and P1D to ‘0’ Drive pins P1B and P1D to ‘1’ Pins P1B and P1D tri-state © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 A shutdown condition is indicated by the ECCPASE (Auto-Shutdown Event Status) bit of the ECCPAS register. If the bit is a ‘ ...
Page 126
... Activity Start of PWM Period DS41365C-page 126 is a condition PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears Preliminary ECCPASE Cleared by Firmware PWM Resumes PWM Resumes © 2009 Microchip Technology Inc. ...
Page 127
... The lower seven bits of the associated PWM1CON register (Register 13-3) sets the delay period in terms of microcontroller instruction cycles ( OSC FIGURE 13-15: EXAMPLE OF HALF-BRIDGE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 FIGURE 13-14: Period Pulse Width (2) P1A td (2) P1B (1) ...
Page 128
... DS41365C-page 128 R/W-0 R/W-0 PDC4 PDC3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared / cycles between the scheduled time when a PWM signal OSC OSC Preliminary R/W-0 R/W-0 R/W-0 PDC2 PDC1 PDC0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 129
... P1A pin is assigned to port pin Note 1: The PWM Steering mode is available only when the CCP1CON register bits CCP1M<3:2> and P1M<1:0> = 00. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Note: The associated TRIS bits must be set to output (‘0’) to enable the pin output driver in order to see the PWM signal on the pin. While the PWM Steering mode is active, CCP1M< ...
Page 130
... Note 1: Port outputs are configured as shown when the CCP1CON register bits P1M<1:0> and CCP1M<3:2> = 11. 2: Single PWM output requires setting at least one of the STRx bits. DS41365C-page 130 P1A pin P1B pin P1C pin P1D pin Preliminary © 2009 Microchip Technology Inc. ...
Page 131
... PORT Data FIGURE 13-18: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRSYNC = 1) PWM STRn P1<D:A> PORT Data © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Figures 13-17 and 13-18 illustrate the timing diagrams of the PWM steering depending on the STRSYNC setting. PORT Data P1n = PWM P1n = PWM ...
Page 132
... TMR1IE 254 TMR3IE 254 — — TMR2IF TMR1IF 254 TMR3IF 254 — — 252 PDC2 PDC1 PDC0 253 PD POR BOR 252 252 252 252 253 253 TRISC1 TRISC0 254 TMR1CS TMR1ON 252 252 TMR3CS TMR3ON 253 © 2009 Microchip Technology Inc. ...
Page 133
... The I C interface supports the following modes in hardware: • Master mode • Multi-Master mode • Slave mode © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 14.2 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes ...
Page 134
... SSPIF interrupt is set. During transmission, double-buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. R-0 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary the SSPBUF is not R-0 R bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 135
... In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 R/W-0 R/W-0 R/W-0 CKP ...
Page 136
... Example 14-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP STATUS register (SSPSTAT) indicates the various status conditions. Preliminary © 2009 Microchip Technology Inc. ...
Page 137
... Shift Register (SSPSR) LSb MSb General I/O Processor 1 © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 14.2.4 TYPICAL CONNECTION Figure 14-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their pro- grammed clock edge and latched on the opposite edge of the clock ...
Page 138
... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit 2 bit 5 bit 4 bit 1 bit 3 bit 2 bit 5 bit 4 bit 3 bit 1 Preliminary give waveforms for SPI ) Clock Modes bit 0 bit 0 bit 0 bit 0 © 2009 Microchip Technology Inc. ...
Page 139
... Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 14.2.7 SLAVE SELECT SYNCHRONIZATION The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled (SSPCON1<3:0> = 0100). When the SS pin is low, transmission and reception are enabled and the SDO pin is driven ...
Page 140
... CKE = 1) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS41365C-page 140 bit 6 bit 3 bit 2 bit 5 bit 4 bit 6 bit 3 bit 2 bit 5 bit 4 Preliminary bit 1 bit 0 bit 0 bit 1 bit 0 bit 0 © 2009 Microchip Technology Inc. ...
Page 141
... SSPSTAT SMP CKE Legend: Shaded cells are not used by the MSSP in SPI mode. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Transmit/Receive Shift register. When all 8 bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. ...
Page 142
... SSPBUF Addr Match and the SSPIF interrupt is set. During transmission, double-buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. Set, Reset S, P bits (SSPSTAT Reg) Preliminary mode operation. The 2 C the SSPBUF is not © 2009 Microchip Technology Inc. ...
Page 143
... This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. 3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the Master mode is active. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 2 C MODE) ...
Page 144
... DS41365C-page 144 2 C MODE) R/W-0 R/W-0 R/W-0 CKP SSPM3 SSPM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2 C conditions were not valid for a trans- /(4 * (SSPADD + 1)) OSC Preliminary R/W-0 R/W-0 SSPM1 SSPM0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 145
... For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). 2: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 2 C MODE) ...
Page 146
... SSPIF, BF, R/W are set). 9. Read the SSPBUF register (clears bit BF) and clear flag bit, SSPIF. 10. Load SSPBUF with byte the slave is to transmit, sets the BF bit. 11. Set the CKP bit to release SCL. Preliminary Addressing © 2009 Microchip Technology Inc. ...
Page 147
... The clock must be released by setting the CKP bit of the SSPCON1 register. See Section 14.3.4 “Clock Stretching” for more detail. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 14.3.3.3 Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set ...
Page 148
... PIC18F1XK22/LF1XK22 2 FIGURE 14-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) DS41365C-page 148 Preliminary © 2009 Microchip Technology Inc. ...
Page 149
... FIGURE 14-9: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Preliminary DS41365C-page 149 ...
Page 150
... PIC18F1XK22/LF1XK22 2 FIGURE 14-10: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) DS41365C-page 150 Preliminary © 2009 Microchip Technology Inc. ...
Page 151
... FIGURE 14-11: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Preliminary DS41365C-page 151 ...
Page 152
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2 C address match 2 (1) C Slave mode, 10-bit Address 2 C address match Preliminary 2 C Slave mode (7-bit or R/W-1 R/W-1 (1) MSK1 MSK0 bit Bit is unknown 2 C address match 2 C address match © 2009 Microchip Technology Inc. ...
Page 153
... ADD<7:0>: Eight Least Significant bits of 10-bit address 7-Bit Slave mode: bit 7-1 ADD<6:0>: 7-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care.” © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 R/W-0 R/W-0 R/W-0 ADD4 ADD3 ADD2 U = Unimplemented bit, read as ‘ ...
Page 154
... UA bit is not set, the module is now configured in Transmit mode and clock stretching is automatic with the hard- ware clearing CKP 7-bit Slave Transmit mode (see Figure 14-11). Preliminary data transfer sequence (see © 2009 Microchip Technology Inc. ...
Page 155
... CKP bit will not violate the minimum high time requirement for SCL (see Figure 14-12). FIGURE 14-12: CLOCK SYNCHRONIZATION TIMING SDA DX SCL CKP WR SSPCON1 © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Master device asserts clock Master device deasserts clock Preliminary DX – 1 DS41365C-page 155 ...
Page 156
... PIC18F1XK22/LF1XK22 2 FIGURE 14-13: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) DS41365C-page 156 Preliminary © 2009 Microchip Technology Inc. ...
Page 157
... FIGURE 14-14: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Preliminary DS41365C-page 157 ...
Page 158
... Acknowledge (Figure 14-15). Address is compared to General Call Address after ACK, set interrupt R ACK Cleared by software SSPBUF is read Preliminary Receiving Data ACK ‘0’ ‘1’ © 2009 Microchip Technology Inc. ...
Page 159
... Generate a Stop condition on SDA and SCL. FIGURE 14-16: MSSP BLOCK DIAGRAM (I SDA SDA In SCL SCL In Bus Collision © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Note: The MSSP module, when configured Master mode, does not allow queueing of events. For instance, the user is not ...
Page 160
... ACKSTAT bit of the SSPCON2 register. 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 11. The user generates a Stop condition by setting the PEN bit of the SSPCON2 register. 12. Interrupt is generated once the Stop condition is complete. Preliminary © 2009 Microchip Technology Inc. ...
Page 161
... The I C interface does not conform to the 400 kHz I 100 kHz) in all details, but may be used with care where higher rates are required by the application. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Table 14-3 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPADD ...
Page 162
... BRG 03h Value BRG Reload DS41365C-page 162 DX – 1 SCL allowed to transition high BRG decrements on Q2 and Q4 cycles 02h 01h 00h (hold off) SCL is sampled high, reload takes place and BRG starts its count Preliminary 03h 02h © 2009 Microchip Technology Inc. ...
Page 163
... Start condition is complete. FIGURE 14-19: FIRST START BIT TIMING Write to SEN bit occurs here SDA SCL © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Note the beginning of the Start condition, the SDA and SCL pins are already sam- pled low during the Start condition, the ...
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... SSPCON2 is disabled until the Repeated Start condition is complete. S bit set by hardware SDA = 1, At completion of Start bit, SCL = 1 hardware clears RSEN bit and sets SSPIF BRG BRG BRG Write to SSPBUF occurs here T BRG Sr = Repeated Start Preliminary 1st bit T BRG © 2009 Microchip Technology Inc. ...
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... WCOL is set and the contents of the buf- fer are unchanged (the write doesn’t occur). WCOL must be cleared by software before the next transmission. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 14.3.10.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit of the SSPCON2 ...
Page 166
... PIC18F1XK22/LF1XK22 2 FIGURE 14-21: I C™ MASTER MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS) DS41365C-page 166 Preliminary © 2009 Microchip Technology Inc. ...
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... FIGURE 14-22: I C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Preliminary DS41365C-page 167 ...
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... BRG SCL brought high after T BRG SDA asserted low before rising edge of clock to setup Stop condition Preliminary (Baud Rate Generator rollover count) later, the PEN bit is BRG WCOL Status Flag ACKEN automatically cleared Cleared in software BRG © 2009 Microchip Technology Inc. ...
Page 169
... FIGURE 14-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA SCL BCLIF © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 14.3.17 MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitra- tion. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a ‘ ...
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... Repeated Start or Stop conditions. SEN cleared automatically because of bus collision. SSP module reset into Idle state. SSPIF and BCLIF are cleared by software SSPIF and BCLIF are cleared by software Preliminary © 2009 Microchip Technology Inc. ...
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... BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION Less than T SDA pulled low by other master. SDA Reset BRG and assert SDA. SCL SEN BCLIF S SSPIF © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 SDA = 0, SCL = BRG BRG SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SDA = 0, SCL = 1 ...
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... Repeated Start condition is complete. Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. Cleared by software T T BRG BRG Preliminary © 2009 Microchip Technology Inc. ‘0’ ‘0’ Interrupt cleared by software ‘0’ ...
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... SCL PEN BCLIF P SSPIF © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD and counts down to 0 ...
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... TMR2IE TMR1IE 254 — TMR3IE — 254 TMR2IF TMR1IF 254 — TMR3IF — 254 2 C Master Mode. 252 252 SSPM1 SSPM0 252 RSEN SEN 252 MSK1 MSK0 254 UA BF 252 — — — 254 © 2009 Microchip Technology Inc. ...
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... SPBRGH SPBRG BRGH BRG16 © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 The EUSART module includes the following capabilities: • Full-duplex asynchronous transmit and receive • Two-character input buffer • One-character output buffer • Programmable 8-bit or 9-bit character length • Address detection in 9-bit mode • ...
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... DS41365C-page 176 MSb Data Stop Recovery F OSC ÷ x16 x64 0 0 FERR 0 Register 15-1, Preliminary CREN OERR RCIDL RSR Register LSb • • • (8) 7 START 1 0 RX9 FIFO RX9D RCREG Register 8 Data Bus RCIF Interrupt RCIE © 2009 Microchip Technology Inc. ...
Page 177
... TX/CK I/O pin as an output. If the TX/CK pin is shared with an analog peripheral the analog I/O function must be disabled by clearing the corresponding ANSEL bit. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Note 1: When the SPEN bit is set the RX/DT I/O pin is automatically configured as an input, ...
Page 178
... CON register are also set 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit. 8. Load 8-bit data into the TXREG register. This will start the transmission. bit 0 bit 1 bit 7/8 Word 1 Preliminary Stop bit © 2009 Microchip Technology Inc. ...
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... SPBRGH EUSART Baud Rate Generator Register, High Byte TXREG EUSART Transmit Register TXSTA CSRC TX9 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 bit 0 bit 1 Word Bit 5 Bit 4 ...
Page 180
... Setting the DTRXP bit to ‘1’ will invert the receive data resulting in low true idle and data bits. The DTRXP bit controls receive data polarity only in Asynchronous mode. In Synchronous mode the DTRXP bit has a different function. Preliminary Receiving Data Receive Data Polarity © 2009 Microchip Technology Inc. ...
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... The error must be cleared by either clearing the CREN bit of the RCSTA register or by resetting the EUSART by clearing the SPEN bit of the RCSTA register. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 15.1.2.7 Receiving 9-bit Characters The EUSART supports 9-bit character reception. When ...
Page 182
... If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. Start bit 7/8 bit 7/8 Stop Stop bit bit 0 bit bit Word 2 Word 1 RCREG RCREG Preliminary Start bit Stop bit 7/8 bit © 2009 Microchip Technology Inc. ...
Page 183
... EUSART Baud Rate Generator Register, High Byte TRISC TRISC7 TRISC6 TXSTA CSRC TX9 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Bit 5 Bit 4 Bit 3 Bit 2 DTRXP CKTXP BRG16 — ...
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... Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. R/W-0 R/W-0 (1) SYNC SENDB U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary feature (see Section 15.3.1 R/W-0 R-1 R/W-0 BRGH TRMT TX9D bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 R/W-0 R/W-0 R-0 CREN ...
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... Auto-Baud Detect mode is enabled (clears when auto-baud is complete Auto-Baud Detect mode is disabled Synchronous mode: Don’t care DS41365C-page 186 R/W-0 R/W-0 U-0 CKTXP BRG16 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 WUE ABDEN bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 187
... TXSTA CSRC TX9 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is Idle before changing the system clock ...
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... F = 11.0592 MHz OSC SPBRG SPBRG Actual % value value Rate Error (decimal) (decimal) — — — — — — — — — — — — 77 9600 0. 10473 0. 19.20k 0. 57.60k 0.00 11 — 115.2k 0.00 5 © 2009 Microchip Technology Inc. ...
Page 189
... Microchip Technology Inc. PIC18F1XK22/LF1XK22 SYNC = 0, BRGH = 1, BRG16 = 4.000 MHz F = 3.6864 MHz OSC OSC SPBRG % Actual % value Rate Error Rate Error (decimal) — — ...
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... F = 1.000 MHz OSC SPBRGH SPBRGH Actual % :SPBRG :SPBRG Rate Error (decimal) (decimal) 3071 300.1 0.04 832 767 1202 0.16 207 383 2404 0.16 103 95 9615 0. 10417 0. 19.23k 0. — — — 7 — — — © 2009 Microchip Technology Inc. ...
Page 191
... SPBRG SPBRGH Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 and SPBRG registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. ...
Page 192
... To ensure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process before setting the WUE bit receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. Preliminary © 2009 Microchip Technology Inc. ...
Page 193
... If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. 2: The EUSART remains in Idle while the WUE bit is set. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Cleared due to User Read of RCREG Q1 ...
Page 194
... Note that following a Break character, the user will typically want to enable the Auto-Baud Detect feature. For both methods, the user can set the ABDEN bit of the BAUDCON register before placing the EUSART in Sleep mode. bit 0 bit 1 bit 11 Break Auto Cleared Preliminary © 2009 Microchip Technology Inc. Stop bit ...
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... One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 15.4.1.2 Clock Polarity A clock polarity option is provided for Microwire compatibility ...
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... PEIE interrupt enable bits 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit. 8. Start transmission by loading data to the TXREG register. bit 2 bit 7 bit 0 bit 1 Word 2 bit 0 bit 2 bit 1 Preliminary bit 7 ‘1’ bit 6 bit 7 © 2009 Microchip Technology Inc. ...
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... EUSART Baud Rate Generator Register, High Byte TRISC TRISC7 TRISC6 TXREG EUSART Transmit Register TXSTA CSRC TX9 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 Bit 5 Bit 4 Bit 3 Bit 2 DTRXP CKTXP BRG16 — ...
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... Read the 8-bit received data by reading the RCREG register. 10 overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. Preliminary © 2009 Microchip Technology Inc. ...
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... EUSART Baud Rate Generator Register, Low Byte SPBRGH EUSART Baud Rate Generator Register, High Byte TXSTA CSRC TX9 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception. © 2009 Microchip Technology Inc. PIC18F1XK22/LF1XK22 bit 1 bit 2 bit 3 bit 4 Bit 5 ...
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... Least Reset Bit 1 Bit 0 Values on page — WUE ABDEN 253 INT0IF RABIF 251 TMR2IP TMR1IP 254 TMR2IE TMR1IE 254 TMR2IF TMR1IF 254 OERR RX9D 253 253 253 TRISC1 TRISC0 254 253 TRMT TX9D 253 © 2009 Microchip Technology Inc. ...