PIC16LF627A-I/SO Microchip Technology, PIC16LF627A-I/SO Datasheet - Page 57

• Manufacturer Part Number: PIC16LF627A-I/SO
• Description: IC MCU FLASH 1KX14 EEPROM 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF627A-I/SO

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• Controller Family/series: PIC16LF
• No. Of I/o's: 16
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 224Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

9.0
The CCP (Capture/Compare/PWM) module contains a
16-bit register which can operate as a 16-bit Capture
register, as a 16-bit Compare register or as a PWM
master/slave Duty Cycle register. Table 9-1 shows the
timer resources of the CCP module modes.
CCP1 Module
Capture/Compare/PWM
comprised of two 8-bit registers: CCPR1L (low byte)
and CCPR1H (high byte). The CCP1CON register
controls the operation of CCP1. All are readable and
writable.
Additional information on the CCP module is available
in the “PIC
ual” (DS33023).
REGISTER 9-1:
© 2009 Microchip Technology Inc.
CAPTURE/COMPARE/PWM
(CCP) MODULE
®
bit 7-6
bit 5-4
bit 3-0
Mid-Range MCU Family Reference Man-
CCP1CON – CCP OPERATION REGISTER (ADDRESS: 17h)
bit 7
Unimplemented: Read as ‘0’
CCP1X:CCP1Y: PWM Least Significant bits
Capture Mode
Compare Mode
PWM Mode
CCP1M<3:0>: CCPx Mode Select bits
0000 = Capture/Compare/PWM off (resets CCP1 module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCP1IF bit is set)
1001 = Compare mode, clear output on match (CCP1IF bit is set)
1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is
1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1
11xx = PWM mode
Legend:
R = Readable bit
-n = Value at POR
Unused
Unused
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
U-0
—
Register1
unaffected)
U-0
—
(CCPR1)
CCP1X
R/W-0
W = Writable bit
‘1’ = Bit is set
is
PIC16F627A/628A/648A
CCP1Y
R/W-0
TABLE 9-1:
CCP Mode
CCP1M3
Compare
Capture
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
PWM
CCP MODE – TIMER
RESOURCE
CCP1M2 CCP1M1 CCP1M0
R/W-0
x = Bit is unknown
Timer Resource
R/W-0
DS40044G-page 57
Timer1
Timer1
Timer2
R/W-0
bit 0