PIC16F689-I/SO Microchip Technology, PIC16F689-I/SO Datasheet - Page 62
![IC PIC MCU FLASH 4KX14 20SOIC](/photos/6/64/66480/150-20-soic_sml.jpg)
PIC16F689-I/SO
Manufacturer Part Number
PIC16F689-I/SO
Description
IC PIC MCU FLASH 4KX14 20SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F690DM-PCTLHS.pdf
(306 pages)
3.PIC16F677-IP.pdf
(2 pages)
4.PIC16F677-IP.pdf
(16 pages)
5.PIC16F677-ISO.pdf
(294 pages)
Specifications of PIC16F689-I/SO
Program Memory Type
FLASH
Program Memory Size
7KB (4K x 14)
Package / Case
20-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
18
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C/SPI/SSP/EUSART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
17
Number Of Timers
2
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163029, DM164120
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT20SO1-1 - SOCKET TRANS ICE 20DIP TO 20SOICXLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILXLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC164039 - MODULE SKT PROMATE II 20DIP/SOIC
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F690DM-PCTLHS PDF datasheet #2
- PIC16F677-IP PDF datasheet #3
- PIC16F677-IP PDF datasheet #4
- PIC16F677-ISO PDF datasheet #5
- Current page: 62 of 294
- Download datasheet (6Mb)
PIC16F631/677/685/687/689/690
4.2
Every PORTA pin on this device family has an
interrupt-on-change option and a weak pull-up option.
RA0 also has an Ultra Low-Power Wake-up option. The
next three sections describe these functions.
4.2.1
The ANSEL and ANSELH registers are used to disable
the input buffers of I/O pins, which allow analog voltages
to be applied to those pins without causing excessive
current. Setting the ANSx bit of a corresponding pin will
cause all digital reads of that pin to return ‘0’ and also
permit analog functions of that pin to operate correctly.
The state of the ANSx bit has no effect on the digital
output function of its corresponding pin. A pin with the
TRISx bit clear and ANSx bit set will operate as a digital
output, together with the analog input function of that
pin. Pins with the ANSx bit set always read ‘0’, which
can cause unexpected behavior when executing read
or write operations on
read-modify-write sequence of all such operations.
4.2.2
Each of the PORTA pins, except RA3, has an
individually configurable internal weak pull-up. Control
bits WPUAx enable or disable each pull-up. Refer to
Register 4-4. Each weak pull-up is automatically turned
off when the port pin is configured as an output. The
pull-ups are disabled on a Power-on Reset by the
RABPU bit of the OPTION register. A weak pull-up is
automatically enabled for RA3 when configured as
MCLR and disabled when RA3 is an I/O. There is no
software control of the MCLR pull-up.
DS41262C-page 60
Additional Pin Functions
ANSEL AND ANSELH REGISTERS
WEAK PULL-UPS
the port
due to the
Preliminary
4.2.3
Each PORTA pin is individually configurable as an
interrupt-on-change pin. Control bits IOCAx enable or
disable the interrupt function for each pin. Refer to
Register 4-6. The interrupt-on-change is disabled on a
Power-on Reset.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTA. The ‘mismatch’ outputs of the last read are
OR’d together to set the PORTA Change Interrupt Flag
bit (RABIF) in the INTCON register (Register 2-6).
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, clears the
interrupt by:
a)
b)
A mismatch condition will continue to set flag bit RABIF.
Reading PORTA will end the mismatch condition and
allow flag bit RABIF to be cleared. The latch holding the
last read value is not affected by a MCLR nor BOR
Reset. After these Resets, the RABIF flag will continue
to be set if a mismatch is present.
Note:
Any read or write of PORTA. This will end the
mismatch condition, then,
Clear the flag bit RABIF.
INTERRUPT-ON-CHANGE
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RABIF
interrupt flag may not get set.
© 2006 Microchip Technology Inc.
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