PIC16F685-I/P Microchip Technology, PIC16F685-I/P Datasheet - Page 8

• Manufacturer Part Number: PIC16F685-I/P
• Description: IC PIC MCU FLASH 4KX14 20DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F685-I/P

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 20-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C/SPI/SSP/EUSART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163029, DV164120
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162061 - HEADER INTRFC MPLAB ICD2 20PINAC164039 - MODULE SKT PROMATE II 20DIP/SOICDM163029 - BOARD PICDEM FOR MECHATRONICSACICE0203 - MPLABICE 20P 300 MIL ADAPTER
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F631/677/685/687/689/690
FIGURE 8-3:
FIGURE 1:
DS80243M-page 8
A4 and previous revisions
FixedRef
CV
C2V
Rev. A5 CCP Output
REF
REN
C12IN0-
C12IN1-
C2IN2-
C2IN3-
C2CH<1:0>
C2IN+
0
1
CCP Output
MUX
SILICON REVISION A4 AND PREVIOUS VS. REVISION A5
CxOUT
COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM
C2R
CxIF
0
1
2
3
0
1
2
MUX
MUX
Uncertainty due to
Note 1:
Q1 cycle delay
2:
3:
C2V
C2V
When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate.
Q1 and Q3 are phases of the four-phase system clock (F
Q1 is held high during Sleep mode.
IN
IN
-
+
C2
C2ON
C2POL
Read CMxCON0
(1)
From TMR1
Q3*RD_CM2CON0
Clock
Q1
D
NRESET
C2OUT
D
EN
Uncertainty due to
Q
Q1 cycle delay
Q
C2SYNC
D
EN
C2POL
CL
0
1
MUX
Q
 2010 Microchip Technology Inc.
Rev. A5: To ECCP
to Timer1 Gate, SR latch
and other peripherals
To ECCP Auto-Shutdown
Auto-Shutdown
Rev. A4 and previous:
RD_CM2CON0
OSC
Read CMxCON0
).
SYNCC2OUT
Set C2IF
Data Bus
To