TS87C54X2-LIC Atmel, TS87C54X2-LIC Datasheet - Page 23
![IC MCU 8BIT 16K OTP 30MHZ 44PQFP](/photos/12/13/121306/ts87c54x2-lic_sml.jpg)
TS87C54X2-LIC
Manufacturer Part Number
TS87C54X2-LIC
Description
IC MCU 8BIT 16K OTP 30MHZ 44PQFP
Manufacturer
Atmel
Series
87Cr
Datasheet
1.TS87C54X2-LIC.pdf
(62 pages)
Specifications of TS87C54X2-LIC
Core Processor
8051
Core Size
8-Bit
Speed
30/20MHz
Connectivity
UART/USART
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
16KB (16K x 8)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-MQFP, 44-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
4431E–8051–04/06
Table 9-3.
Reset Value = 0000 0000b
Bit addressable
Number
FE/SM0
Bit
7
6
5
4
3
2
1
0
7
Mnemonic
SM0
SM1
SM2
REN
RB8
TB8
Bit
FE
SCON Register
SCON - Serial Control Register (98h)
TI
RI
SM1
6
Framing Error bit (SMOD0=1)
SMOD0 must be set to enable access to the FE bit
Serial port Mode bit 0
SMOD0 must be cleared to enable access to the SM0 bit
Serial port Mode bit 1
Serial port Mode 2 bit / Multiprocessor Communication Enable bit
1. This bit should be cleared in mode 0.
Reception Enable bit
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3.
Receiver Bit 8 / Ninth bit received in modes 2 and 3
Transmit Interrupt flag
the other
Receive Interrupt flag
the other modes.
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
Refer to SM1 for serial port mode selection.
SM0
0
0
1
1
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode
Clear to disable serial reception.
Set to enable serial reception.
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 9-2. and Figure 9-3. in
SM2
5
SM1Mode
0
1
0
1
REN
Description Baud Rate
0
1
2
3
modes.
4
Shift RegisterF
8-bit UARTVariable
9-bit UARTF
9-bit UARTVariable
TB8
3
Description
XTAL
XTAL
AT/TS8xC54/8X2
RB8
/64 or F
2
/12 (/6 in X2 mode)
XTAL
/32 (/32, /16 in X2 mode)
TI
1
RI
0
23