ATTINY85-20MU Atmel, ATTINY85-20MU Datasheet - Page 7
![IC MCU AVR 8K FLASH 20MHZ 20-QFN](/photos/6/87/68751/313-20-qfn_sml.jpg)
ATTINY85-20MU
Manufacturer Part Number
ATTINY85-20MU
Description
IC MCU AVR 8K FLASH 20MHZ 20-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY25-20MU.pdf
(236 pages)
Specifications of ATTINY85-20MU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-MLF®, QFN
Processor Series
ATTINY8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
USI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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4. AVR CPU Core
4.1
4.2
2586M–AVR–07/10
Introduction
Architectural Overview
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
Figure 4-1.
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the Program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruc-
tion is pre-fetched from the Program memory. This concept enables instructions to be executed
in every clock cycle. The Program memory is In-System Reprogrammable Flash memory.
Control Lines
Instruction
Instruction
Program
Memory
Block Diagram of the AVR Architecture
Register
Decoder
Flash
Program
Counter
and Control
EEPROM
Registrers
I/O Lines
Purpose
General
SRAM
Data Bus 8-bit
Status
32 x 8
Data
ALU
I/O Module 2
Comparator
I/O Module1
I/O Module n
Watchdog
Interrupt
Timer
Analog
Unit
7
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