PIC16F882-I/SO Microchip Technology, PIC16F882-I/SO Datasheet - Page 174

• Manufacturer Part Number: PIC16F882-I/SO
• Description: IC PIC MCU FLASH 2KX14 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F882-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: EUSART/MSSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM164120-3
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F822/883/884/886/887
FIGURE 12-12:
TABLE 12-8:
DS41291C-page 172
BAUDCTL ABDOVF
INTCON
PIE1
PIR1
RCREG
RCSTA
SPBRG
SPBRGH
TRISC
TXREG
TXSTA
Legend:
(SCKP = 0)
(SCKP = 1)
(Interrupt)
Note:
Name
TX/CK pin
TX/CK pin
CREN bit
bit SREN
SREN bit
RCIF bit
RXREG
RX/DT
Write to
Read
pin
x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Reception.
EUSART Receive Data Register
EUSART Transmit Data Register
‘0’
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TRISC7
BRG15
CSRC
SPEN
BRG7
Bit 7
GIE
—
—
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
TRISC6
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
BRG14
RCIDL
BRG6
ADIE
PEIE
ADIF
Bit 6
RX9
TX9
bit 0
TRISC5
BRG13
SREN
BRG5
TXEN
RCIE
RCIF
Bit 5
T0IE
—
bit 1
TRISC4
BRG12
CREN
SCKP
BRG4
SYNC
INTE
Bit 4
TXIE
TXIF
bit 2
Preliminary
ADDEN
TRISC3
SENDB
BRG16
BRG11
SSPIE
SSPIF
BRG3
RBIE
Bit 3
bit 3
CCP1IE
CCP1IF
TRISC2
BRG10
BRGH
FERR
BRG2
Bit 2
T0IF
—
bit 4
TMR2IE
TMR2IF
TRISC1
OERR
TRMT
BRG1
BRG9
WUE
Bit 1
INTF
bit 5
TMR1IE
TMR1IF
TRISC0
ABDEN
RX9D
BRG0
BRG8
TX9D
Bit 0
RBIF
© 2006 Microchip Technology Inc.
bit 6
01-0 0-00
0000 000x
-000 0000
-000 0000
0000 0000
0000 000x
0000 0000
0000 0000
1111 1111
0000 0000
0000 0010
POR, BOR
Value on
bit 7
01-0 0-00
0000 000x
-000 0000
-000 0000
0000 0000
0000 000x
0000 0000
0000 0000
1111 1111
0000 0000
0000 0010
Value on
all other
Resets
‘0’