ATTINY45V-10XU Atmel, ATTINY45V-10XU Datasheet - Page 70

• Manufacturer Part Number: ATTINY45V-10XU
• Description: IC MCU AVR 4K FLASH 10MHZ 8TSSOP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY45V-10XU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-TSSOP
• Processor Series: ATtiny
• Core: AVR
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI, USI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.4
70
Counter Unit
ATtiny25/45/85
Figure 11-3. Timer/Counter0 Prescaler
The synchronization logic on the input pins (T0) in
69.
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
11-4
Figure 11-4. Counter Unit Block Diagram
Signal description (internal signals):
PSR10
clk
shows a block diagram of the counter and its surroundings.
count
direction
clear
clk
top
bottom
T0
I/O
Tn
DATA BUS
Synchronization
TCNTn
Increment or decrement TCNT0 by 1.
Select between increment and decrement.
Clear TCNT0 (set all bits to zero).
Timer/Counter clock, referred to as clk
Signalize that TCNT0 has reached maximum value.
Signalize that TCNT0 has reached minimum value (zero).
Clear
direction
count
clear
bottom
Control Logic
Figure 11-3
top
TOVn
(Int.Req.)
clk
Tn
is shown in
Clock Select
clk
( From Prescaler )
T0
Detector
Edge
T0
in the following.
Figure 11-2 on page
2586M–AVR–07/10
Figure
Tn