PIC16F690-I/SS Microchip Technology, PIC16F690-I/SS Datasheet - Page 124
![IC PIC MCU FLASH 4KX14 20SSOP](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16F690-I/SS
Manufacturer Part Number
PIC16F690-I/SS
Description
IC PIC MCU FLASH 4KX14 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F690DM-PCTLHS.pdf
(306 pages)
3.PIC16F677-IP.pdf
(16 pages)
4.PIC16F677-ISO.pdf
(294 pages)
Specifications of PIC16F690-I/SS
Program Memory Type
FLASH
Program Memory Size
7KB (4K x 14)
Package / Case
20-SSOP
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C/SPI/SSP/EUSART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
17
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-1, DM163029
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOPXLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPPIC16F690DM-PCTLHS - BOARD DEMO PICTAIL HUMIDITY SNSRAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC164307 - MODULE SKT FOR PM3 28SSOP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F690-I/SS
Manufacturer:
IR
Quantity:
1 569
Part Number:
PIC16F690-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC16F631/677/685/687/689/690
10.1.2
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD
control bit of the EECON1 register, and then set control
bit RD. The data is available at the very next cycle, in
the EEDAT register; therefore, it can be read in the next
instruction. EEDAT will hold this value until another
read or until it is written to by the user (during a write
operation).
EXAMPLE 10-1:
EXAMPLE 10-2:
DS41262C-page 122
BANKSEL EEADR
MOVF
MOVWF
BANKSEL EECON1
BCF
BSF
BANKSEL EEDAT
MOVF
BCF
BANKSEL EEADR
MOVF
MOVWF
MOVF
MOVWF
BANKSEL EECON1
BCF
BSF
BCF
BTFSC
GOTO
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
SLEEP
BCF
BANKSEL 0x00
DATA_EE_ADDR, W;
EEADR
EECON1, EEPGD ;Point to DATA memory
EECON1, RD
EEDAT, W
STATUS, RP1
READING THE DATA EEPROM
MEMORY
DATA_EE_ADDR, W;
EEADR
DATA_EE_DATA, W;
EEDAT
EECON1, EEPGD
EECON1, WREN
INTCON, GIE
INTCON, GIE
$-2
55h
EECON2
AAh
EECON2
EECON1, WR
INTCON, GIE
EECON1, WREN
DATA EEPROM READ
DATA EEPROM WRITE
;Bank 0
;EE Read
;
;W = EEDAT
;
;Data Memory
;Address to read
;
;
;Data Memory Address to write
;Data Memory Value to write
;
;Point to DATA memory
;Enable writes
;Disable INTs.
;SEE AN576
;
;Write 55h
;
;Write AAh
;Set WR bit to begin write
;Enable INTs.
;Wait for interrupt to signal write complete (optional)
;Disable writes
;Bank 0
Preliminary
10.1.3
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDAT register. Then the user must follow a
specific sequence to initiate the write for each byte.
The write will not initiate if the above sequence is not
followed exactly (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. Interrupts
should be disabled during this code segment.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
WRITING TO THE DATA EEPROM
MEMORY
© 2006 Microchip Technology Inc.