PIC16F882-I/SS Microchip Technology, PIC16F882-I/SS Datasheet - Page 195

• Manufacturer Part Number: PIC16F882-I/SS
• Description: IC PIC MCU FLASH 2KX14 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F882-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 28-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: EUSART/MSSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM164120-3
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164307 - MODULE SKT FOR PM3 28SSOPXLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.4.3
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset, or when the MSSP module is disabled.
Control of the I
set, or the bus is idle, with both the S and P bits clear.
In Master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start condition
FIGURE 13-10:
© 2009 Microchip Technology Inc.
SDA
SCL
Note: I/O pins have diode protection to V
MASTER MODE
2
C bus may be taken when the P bit is
MSSP BLOCK DIAGRAM (I
SDA In
Bus Collision
SCL In
Read
DD
MSb
and V
Write Collision Detect
PIC16F882/883/884/886/887
Start bit, Stop bit,
End of XMIT/RCV
State Counter for
Clock Arbitration
Start bit Detect
Stop bit Detect
Acknowledge
Generate
SS
SSPBUF
SSPSR
.
2
C™ MASTER MODE)
LSb
Write
13.4.4
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON and by setting the
SSPEN bit. Once Master mode is enabled, the user
has the following six options:
1.
2.
3.
4.
5.
6.
Clock
Data Bus
Shift
Note:
Internal
Assert a Start condition on SDA and SCL.
Assert a Repeated Start condition on SDA and
SCL.
Write
transmission of data/address.
Generate a Stop condition on SDA and SCL.
Configure the I
Generate an Acknowledge condition at the end
of a received byte of data.
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
The MSSP module, when configured in I
Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
imitate transmission, before the Start
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
I
to
2
C™ MASTER MODE SUPPORT
the
2
C port to receive data.
SSPBUF
SSPADD<6:0>
SSPM<3:0>
Baud
Rate
Generator
register
DS41291F-page 193
initiating
2
C