AT89S52-24PU Atmel, AT89S52-24PU Datasheet - Page 22

• Manufacturer Part Number: AT89S52-24PU
• Description: IC MCU 8K FLASH 24MHZ 40-DIP
• Manufacturer: Atmel
• Series: 89Sr

Specifications of AT89S52-24PU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Package: 40PDIP
• Device Core: 8051
• Family Name: 89S
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 32
• Interface Type: UART
• Number Of Timers: 3
• Processor Series: AT89x
• Core: 8051
• Data Ram Size: 256 B
• Maximum Clock Frequency: 24 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89ISP
• Minimum Operating Temperature: - 40 C
• Eeprom Memory: 0 Bytes
• Input Output: 32
• Interface: UART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 8K Bytes
• Timers: 3-16-bit
• Voltage, Range: 4-5.5 V
• Cpu Family: 89S
• Device Core Size: 8b
• Frequency (max): 24MHz
• Total Internal Ram Size: 256Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 40
• Controller Family/series: (8051) 8052
• No. Of I/o's: 32
• Ram Memory Size: 256Byte
• Cpu Speed: 24MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q2897580

19. Programming the Flash – Serial Mode
20. Serial Programming Algorithm
21. Serial Programming Instruction Set
22
AT89S52
The Code memory array can be programmed using the serial ISP interface while RST is pulled
to V
set high, the Programming Enable instruction needs to be executed first before other operations
can be executed. Before a reprogramming sequence can occur, a Chip Erase operation is
required.
The Chip Erase operation turns the content of every memory location in the Code array into
FFH.
Either an external system clock can be supplied at pin XTAL1 or a crystal needs to be connected
across pins XTAL1 and XTAL2. The maximum serial clock (SCK) frequency should be less than
1/16 of the crystal frequency. With a 33 MHz oscillator clock, the maximum SCK frequency is
2 MHz.
To program and verify the AT89S52 in the serial programming mode, the following sequence is
recommended:
If a crystal is not connected across pins XTAL1 and XTAL2, apply a 3 MHz to 33 MHz clock to
XTAL1 pin and wait for at least 10 milliseconds.
Power-off sequence (if needed):
Data Polling: The Data Polling feature is also available in the serial mode. In this mode, during
a write cycle an attempted read of the last byte written will result in the complement of the MSB
of the serial output byte on MISO.
The Instruction Set for Serial Programming follows a 4-byte protocol and is shown in
1. Power-up sequence:
2. Enable serial programming by sending the Programming Enable serial instruction to pin
3. The Code array is programmed one byte at a time in either the Byte or Page mode. The
4. Any memory location can be verified by using the Read instruction which returns the
5. At the end of a programming session, RST can be set low to commence normal device
1. Set XTAL1 to “L” (if a crystal is not used).
2. Set RST to “L”.
3. Turn V
CC
a. Apply power between VCC and GND pins.
b. Set RST pin to “H”.
MOSI/P1.5. The frequency of the shift clock supplied at pin SCK/P1.7 needs to be less
than the CPU clock at XTAL1 divided by 16.
write cycle is self-timed and typically takes less than 0.5 ms at 5V.
content at the selected address at serial output MISO/P1.6.
operation.
. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RST is
CC
power off.
1919D–MICRO–6/08
Table
24-1.