ATTINY13A-MMU Atmel, ATTINY13A-MMU Datasheet - Page 52

• Manufacturer Part Number: ATTINY13A-MMU
• Description: IC MCU AVR 1K FLASH 20MHZ 10-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY13A-MMU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (512 x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 10-MLF®, 10-DFN
• Processor Series: ATTINY1x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAKSTK511
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• Package: 10MLF EP
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• For Use With: ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

52
ATtiny13A
Figure 10-3. Synchronization when Reading an Externally Applied Pin value
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-
cated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed
between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indi-
cated in
positive edge of the clock. In this case, the delay tpd through the synchronizer is one system
clock period.
Figure 10-4. Synchronization when Reading a Software Assigned Pin Value
INSTRUCTIONS
INSTRUCTIONS
SYSTEM CLK
SYNC LATCH
SYSTEM CLK
SYNC LATCH
Figure 10-4 on page
PINxn
PINxn
r17
r16
r17
out PORTx, r16
52. The out instruction sets the “SYNC LATCH” signal at the
XXX
t
pd, max
0x00
0x00
XXX
nop
t
pd
t
0xFF
pd, min
in r17, PINx
in r17, PINx
8126E–AVR–07/10
0xFF
0xFF