PIC16F687-I/SS Microchip Technology, PIC16F687-I/SS Datasheet - Page 111
![IC PIC MCU FLASH 2KX14 20SSOP](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16F687-I/SS
Manufacturer Part Number
PIC16F687-I/SS
Description
IC PIC MCU FLASH 2KX14 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F690DM-PCTLHS.pdf
(306 pages)
3.PIC16F677-IP.pdf
(2 pages)
4.PIC16F677-IP.pdf
(16 pages)
5.PIC16F677-ISO.pdf
(294 pages)
Specifications of PIC16F687-I/SS
Program Memory Type
FLASH
Program Memory Size
3.5KB (2K x 14)
Package / Case
20-SSOP
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
18
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
I2C/SPI/SSP/EUSART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
17
Number Of Timers
2
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163029, DV164120
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOPXLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC164307 - MODULE SKT FOR PM3 28SSOP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F687-I/SS
Manufacturer:
IXYS
Quantity:
4 592
- PIC16F616T-ISL PDF datasheet
- PIC16F690DM-PCTLHS PDF datasheet #2
- PIC16F677-IP PDF datasheet #3
- PIC16F677-IP PDF datasheet #4
- PIC16F677-ISO PDF datasheet #5
- Current page: 111 of 294
- Download datasheet (6Mb)
TABLE 9-1:
FIGURE 9-2:
9.1.5
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC interrupt flag is the ADIF bit in the
PIR1 register. The ADC interrupt enable is the ADIE bit
in the PIE1 register. The ADIF bit must be cleared in
software.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the global interrupt must be disabled. If the
global interrupt is enabled, execution will switch to the
interrupt service routine.
Please see Section 9.1.5 “Interrupts” for more
information.
© 2006 Microchip Technology Inc.
Legend: Shaded cells are outside of recommended range.
Note 1:
ADC Clock Source
Note:
F
F
F
2:
3:
4:
F
F
F
OSC
OSC
OSC
OSC
OSC
OSC
F
ADC Clock Period (T
RC
The F
These values violate the minimum required T
For faster conversion times, the selection of another clock source is recommended.
When the device frequency is greater than 1 MHz, the F
conversion will be performed during Sleep.
INTERRUPTS
The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
T
/16
/32
/64
/2
/4
/8
CY
Set GO/DONE bit
Holding Capacitor is disconnected from analog input (typically 100 ns)
to T
RC
ADC CLOCK PERIOD (T
AD
source has a typical T
Conversion Starts
ANALOG-TO-DIGITAL CONVERSION T
T
AD
1 T
ADCS<2:0>
AD
b9
AD
000
100
001
101
010
110
x11
2 T
)
PIC16F631/677/685/687/689/690
AD
b8
3 T
AD
AD
b7
time of 4 s for V
AD
4 T
) V
2-6 s
100 ns
200 ns
400 ns
800 ns
20 MHz
Preliminary
1.6 s
3.2 s
AD
b6
S
5 T
. DEVICE OPERATING FREQUENCIES (V
(1,4)
AD
(2)
(2)
(2)
(2)
AD
b5
time.
6 T
DD
ADRESH and ADRESL registers are loaded,
GO bit is cleared,
ADIF bit is set,
Holding capacitor is connected to analog input
AD
b4
> 3.0V.
7 T
2-6 s
RC
250 ns
500 ns
Device Frequency (F
1.0 s
8.0 s
AD
8 MHz
2.0 s
4.0 s
clock source is only recommended if the
AD
b3
CYCLES
(1,4)
8 T
(2)
(3)
(2)
(2)
AD
b2
9
T
AD
b1
2-6 s
16.0 s
500 ns
1.0 s
8.0 s
10 T
4 MHz
2.0 s
4.0 s
OSC
AD
b0
(1,4)
(2)
(3)
(2)
(3)
11
)
DS41262C-page 109
DD
2-6 s
16.0 s
32.0 s
64.0 s
8.0 s
1 MHz
2.0 s
4.0 s
> 3.0V)
(1,4)
(3)
(3)
(3)
(3)
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