PIC16F688-I/SL Microchip Technology, PIC16F688-I/SL Datasheet - Page 150

• Manufacturer Part Number: PIC16F688-I/SL
• Description: IC PIC MCU FLASH 4KX14 14SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F688-I/SL

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 1
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT14SO-1 - SOCKET TRANSITION 14SOIC 150/208AC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PICmicro MID-RANGE MCU FAMILY
9.6
DS31009A-page 9-10
PORTE and the TRISE Register
PORTE can be up to an 8-bit port with Schmitt Trigger input buffers. Each pin is individually con-
figurable as an input or output.
Example 9-5: Initializing PORTE
Figure 9-8: Typical PORTE Block Diagram (in I/O Port Mode)
Data Bus
WR PORT
WR TRIS
RD PORT
Note: I/O pins have protection diodes to V
Note:
CLRF
CLRF
BSF
MOVLW
MOVWF
On some devices with PORTE, the upper bits of the TRISE register are used for the
Parallel Slave Port control and status bits.
STATUS
PORTE
STATUS, RP0
0x03
TRISE
TRIS Latch
Data Latch
D
D
CK
CK
; Bank0
; Initialize PORTE by clearing output
;
; Select Bank1
; Value used to initialize data direction
; PORTE<1:0> = inputs, PORTE<7:2> = outputs
Q
Q
Q
Q
RD TRIS
data latches
DD
and V
SS
.
Q
EN
D
1997 Microchip Technology Inc.
Schmitt
Trigger
input
buffer
I/O pin