AT89S51-24PU Atmel, AT89S51-24PU Datasheet - Page 4

IC MCU 4K FLASH 24MHZ 40-DIP

AT89S51-24PU

Manufacturer Part Number
AT89S51-24PU
Description
IC MCU 4K FLASH 24MHZ 40-DIP
Manufacturer
Atmel
Series
89Sr
Datasheets

Specifications of AT89S51-24PU

Core Processor
8051
Core Size
8-Bit
Speed
24MHz
Connectivity
UART/USART
Peripherals
WDT
Number Of I /o
32
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
ISP/UART
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
32
Number Of Timers
2
Operating Supply Voltage
4 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
AT89ISP
Minimum Operating Temperature
- 40 C
Controller Family/series
(8051) 8052
No. Of I/o's
32
Ram Memory Size
128Byte
Cpu Speed
24MHz
No. Of Timers
2
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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4. Pin Description
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4
VCC
GND
VDD
PWRVDD
PWRGND
Port 0
Port 1
AT89S51
Supply voltage (all packages except 42-PDIP).
Ground (all packages except 42-PDIP; for 42-PDIP GND connects only the logic core and the
embedded program memory).
Supply voltage for the 42-PDIP which connects only the logic core and the embedded program
memory.
Supply voltage for the 42-PDIP which connects only the I/O Pad Drivers. The application board
MUST connect both VDD and PWRVDD to the board supply voltage.
Ground for the 42-PDIP which connects only the I/O Pad Drivers. PWRGND and GND are
weakly connected through the common silicon substrate, but not through any metal link. The
application board MUST connect both GND and PWRGND to the board ground.
Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL
inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.
Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses
to external program and data memory. In this mode, P0 has internal pull-ups.
Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur-
ing program verification. External pull-ups are required during program verification.
Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can
sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the inter-
nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low
will source current (I
Port 1 also receives the low-order address bytes during Flash programming and verification.
Port Pin
P1.5
P1.6
P1.7
IL
) because of the internal pull-ups.
Alternate Functions
MOSI (used for In-System Programming)
MISO (used for In-System Programming)
SCK (used for In-System Programming)
2487C–MICRO–03/05

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