PIC16F59-I/P Microchip Technology, PIC16F59-I/P Datasheet - Page 50
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PIC16F59-I/P
Manufacturer Part Number
PIC16F59-I/P
Description
IC PIC MCU FLASH 2KX12 40DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Specifications of PIC16F59-I/P
Core Size
8-Bit
Program Memory Size
3KB (2K x 12)
Core Processor
PIC
Speed
20MHz
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Type
FLASH
Ram Size
134 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC16F
No. Of I/o's
32
Ram Memory Size
134Byte
Cpu Speed
20MHz
No. Of Timers
1
Package
40PDIP
Device Core
PIC
Family Name
PIC16
Maximum Speed
20 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
32
Number Of Timers
1
Processor Series
PIC16F
Core
PIC
Data Ram Size
134 B
Maximum Clock Frequency
20 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
DV164101, DV164120
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164001 - MODULE SKT PROMATEII 18/28DIP
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F59-I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
PIC16F59-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC16F5X
IORLW
Syntax:
Operands:
Operation:
Status Affected: Z
Encoding:
Description:
Words:
Cycles:
Example:
IORWF
Syntax:
Operands:
Operation:
Status Affected: Z
Encoding:
Description:
Words:
Cycles:
Example:
DS41213D-page 48
Before Instruction
After Instruction
Before Instruction
After Instruction
W
W
Z
RESULT
W
RESULT
W
Z
=
=
=
0x9A
0xBF
0
Inclusive OR literal with W
[ label ]
0 ≤ k ≤ 255
(W) .OR. (k) → (W)
The contents of the W register are
OR’ed with the eight-bit literal ‘k’.
The result is placed in the W
register.
1
1
IORLW 0x35
Inclusive OR W with f
[ label ]
0 ≤ f ≤ 31
d ∈ [0,1]
(W).OR. (f) → (dest)
Inclusive OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is ‘1’,
the result is placed back in
register ‘f’.
1
1
IORWF
1101
0001
=
=
=
=
=
0x13
0x91
0x13
0x93
0
IORLW k
IORWF
kkkk
00df
RESULT, 0
kkkk
ffff
f, d
MOVF
Syntax:
Operands:
Operation:
Status Affected: Z
Encoding:
Description:
Words:
Cycles:
Example:
MOVLW
Syntax:
Operands:
Operation:
Status Affected: None
Encoding:
Description:
Words:
Cycles:
Example:
After Instruction
After Instruction
W
W
=
=
Move f
[ label ]
0 ≤ f ≤ 31
d ∈ [0,1]
(f) → (dest)
The contents of register ‘f’ is
moved to destination ‘d’. If ‘d’ is ‘0’,
destination is the W register. If ‘d’
is ‘1’, the destination is file
register ‘f’. ‘d’ is ‘1’ is useful to test
a file register since Status flag Z is
affected.
1
1
MOVF
Move Literal to W
[ label ]
0 ≤ k ≤ 255
k → (W)
The eight-bit literal ‘k’ is loaded
into the W register.
1
1
MOVLW 0x5A
0010
1100
value in FSR register
0x5A
© 2007 Microchip Technology Inc.
FSR,
MOVF f, d
MOVLW k
00df
kkkk
0
ffff
kkkk