PIC12F675T-E/MF Microchip Technology, PIC12F675T-E/MF Datasheet - Page 3
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PIC12F675T-E/MF
Manufacturer Part Number
PIC12F675T-E/MF
Description
IC MCU CMOS 1K FLASH W/AD 8-DFN
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Datasheets
1.PIC12F629T-ISN.pdf
(136 pages)
2.PIC12F629T-ISN.pdf
(8 pages)
3.PIC12F629T-ISN.pdf
(24 pages)
Specifications of PIC12F675T-E/MF
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
8-DFN
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT08DFN2 - SOCKET TRANSITION ICE 14DIP/8DFNXLT08DFN - SOCKET TRANSITION ICE 8DFNAC164032 - ADAPTER PICSTART PLUS 8DFN/DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Other names
PIC12F675-E/MFTR
PIC12F675-E/MFTR
PIC12F675T-E/MFTR
PIC12F675-E/MFTR
PIC12F675T-E/MFTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12F675T-E/MF
Manufacturer:
Microchip
Quantity:
5 029
Silicon Errata Issues
1. Module: Data EEPROM Memory
© 2009 Microchip Technology Inc.
Note:
The EEIF flag may be cleared inadvertently when
performing operations on the PIR1 register,
simultaneously with the completion of an EEPROM
write. This condition occurs when the EEPROM
write timer completes at the same moment that the
PIR1 register operation is executed. Register
operations are those that have the PIR1 register as
the destination and include, but are not limited to,
BSF, BCF, ANDWF, IORWF and XORWF.
Work around
1. Avoid operations on the PIR1 register when
2. Poll the WR bit (EECON1<1>) to determine
3. Use a timer interrupt to catch any instances
4. If periodic interrupts are occurring in addition to
Affected Silicon Revisions
A9
X
writing to the EEPROM memory.
when the write is complete.
when the EEIF flag is inadvertently cleared.
The timer interrupt should be set longer than
8 ms. If EEIF fails, then the timer interrupt
occurs as a default time out. The WR and
WRERR flags are checked as part of the timer
Interrupt
EEPROM write success.
the EEIF interrupts, then use a secondary flag
to sense write completion. The secondary flag
is set whenever EEPROM writes are active. An
EEPROM write completion is indicated when
the secondary flag is set and the WR flag is
clear.
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (B0).
B0
X
Service
Routine
to
verify
the
2. Module: Power-on Reset (Rising V
The PIC12F629/675 Power-on Reset (POR)
circuitry is sensitive to a low V
to release the Reset if V
voltage after dropping to a very low level.
The sensitive V
drops into an out-of-specification voltage region
below the Brown-out Detect threshold and then
recovers to a normal operating condition. The
voltage region that can cause the problem is
dependant upon temperature with the region
growing as the temperature drops. A typical region
is between 0.5 and 0.7V at -25°C. Below the region,
the POR operates correctly. Above the region, the
POR is inactive per the data sheet. Inside the
region, the POR will assert Reset and will not
release Reset until power is removed and V
reaches V
other Reset circuits (see Figure 9-4 of the data
sheet), activating BOR or using the MCLR input will
not eliminate the problem.
Work around
To resolve this problem, the application must be
designed to assure that V
described as D003 V
“Electrical Specifications” of the Device Data
Sheet (DS41190F).
Affected Silicon Revisions
A9
X
B0
SS
Detect)
PIC12F629/675
. Because the POR is independent of
DD
condition occurs when V
DD
POR
DD
returns to an operational
reaches V
DD
in Section 12.0
level and may fail
DS80125H-page 3
SS
DD
. This is
DD
DD