PIC12F519-I/SN Microchip Technology, PIC12F519-I/SN Datasheet - Page 4

• Manufacturer Part Number: PIC12F519-I/SN
• Description: IC PIC MCU FLASH 1KX12 8SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F519-I/SN

• Program Memory Type: FLASH
• Program Memory Size: 1.5KB (1K x 12)
• Package / Case: 8-SOIC (3.9mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Ram Size: 41 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC12F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 41 B
• Interface Type: USB
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• Height: 1.25 mm
• Length: 4.9 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 3.9 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC12F519
3.1.2.1
After receiving this command, the device will clock in
14 bits as a “data word” when 16 cycles are applied, as
described previously. Because this is a 12-bit core, the
FIGURE 3-2:
3.1.2.2
After receiving this command, the chip will transmit
data bits out of the memory currently accessed starting
with the second rising edge of the clock input. The RB0
pin will go into Output mode on the second rising clock
FIGURE 3-3:
DS41316B-page 4
RB0
(ICSPCLK)
(ICSPDAT)
RB1
RB0
(ICSPDAT)
(ICSPCLK)
RB1
Load Data
Read Data
1
1
LOAD DATA COMMAND (PROGRAM/VERIFY)
READ DATA FROM PROGRAM MEMORY COMMAND
0
0
1
T
SET
2
0
1
2
1
1
T
3
SET
T
0
3
HLD
Input
1
T
1
HLD
4
0
0
4
1
5
5
x
x
T
6
DLY
x
6
x
T
T
1
T
DLY
DLY
DLY
2
two MSbs of the data word are ignored. A timing
diagram for the Load Data command is shown in
Figure 3-2.
2
edge and it will revert back to Input mode (high-imped-
ance) after the 16th rising edge. Because this is a 12-
bit core, the two MSbs will read as ‘1’. A timing diagram
of this command is shown in Figure 3-3.
1
1
strt_bit
1
strt_bit
2
2
LSb
LSb
T
3
T
SET
DLY
3
-+
T
1
3
HLD
4
1
4
Output
© 2007 Microchip Technology Inc.
5
5
15
MSb
15
16
MSb
stp_bit
16
stp_bit
Input