EPF6010A ALTERA [Altera Corporation], EPF6010A Datasheet
EPF6010A
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EPF6010A Summary of contents
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... System-level features – – – – – – Table 1. FLEX 6000 Device Features Feature EPF6010A Typical gates (1) 10,000 Logic elements (LEs) Maximum I/O pins Supply voltage (V ) 3.3 V CCINT Note: (1) The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 14,000 gates in addition to the listed typical gates. ...
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... EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, VeriBest, and Viewlogic Table 2. FLEX 6000 Package Options & I/O Pin Count Device 100-Pin 100-Pin TQFP FineLine BGA EPF6010A 71 EPF6016 EPF6016A 81 81 EPF6024A 2 Individual tri-state output enable control for each pin ...
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General The Altera a low-cost alternative to high-volume gate array designs. FLEX 6000 Description devices are based on the OptiFLEX architecture, which minimizes die size while maintaining high performance and routability. The devices have reconfigurable SRAM elements, which give designers ...
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FLEX 6000 Programmable Logic Device Family Data Sheet Table 4 Table 4. FLEX 6000 Device Performance for Complex Designs Application 8-bit, 16-tap parallel finite impulse response (FIR) filter 8-bit, 512-point fast Fourier transform (FFT) function a16450 universal asynchronous receiver/transmitter (UART) ...
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Functional The FLEX 6000 OptiFLEX architecture consists of logic elements (LEs). Each LE includes a 4-input look-up table (LUT), which can implement any Description 4-input function, a register, and dedicated paths for carry and cascade chain functions. Because each LE ...
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FLEX 6000 Programmable Logic Device Family Data Sheet Figure 1. OptiFLEX Architecture Block Diagram Column FastTrack IOEs Interconnect FLEX 6000 devices provide four dedicated, global inputs that drive the control inputs of the flipflops to ensure efficient distribution of high- ...
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The interleaved LAB structure—an innovative feature of the FLEX 6000 architecture—allows each LAB to drive two local interconnects. This feature minimizes the use of the FastTrack Interconnect, providing higher performance. An LAB can drive 20 LEs in adjacent LABs via ...
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FLEX 6000 Programmable Logic Device Family Data Sheet Figure 3. LAB Control Signals The dedicated input signals can drive the clock and asynchronous clear signals. Dedicated Inputs Input signals to the first LAB (i.e can ...
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Figure 4. Logic Element data1 Look-Up data2 able T data3 (LUT) data4 labctrl1 Clear/ Preset labctrl2 Logic Chip-Wide Reset Clock Select labctrl3 labctrl4 The programmable flipflop in the LE can be configured for operation. The ...
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FLEX 6000 Programmable Logic Device Family Data Sheet Carry Chain The carry chain provides a very fast (0.1 ns) carry-forward function between LEs. The carry-in signal from a lower-order bit drives forward into the higher-order bit via the carry chain, ...
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Figure 5. Carry Chain Operation Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet Carry-In LUT Carry Chain LUT Carry Chain LUT Carry Chain LUT Carry Chain s1 Register LE 2 Register s2 ...
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FLEX 6000 Programmable Logic Device Family Data Sheet Cascade Chain The cascade chain enables the FLEX 6000 architecture to implement very wide fan-in functions. Adjacent LUTs can be used to implement portions of the function in parallel; the cascade chain ...
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Figure 6. Cascade Chain Operation AND Cascade Chain d[3..0] LUT d[7..4] LUT d[(4 n -1)..4( n -1)] LUT LE Operating Modes The FLEX 6000 LE can operate in one of the following three modes: ■ Normal mode ■ Arithmetic mode ...
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FLEX 6000 Programmable Logic Device Family Data Sheet Figure 7. LE Operating Modes Normal Mode Carry-In data1 data2 4-Input LUT data3 data4 Arithmetic Mode Carry-In data1 3-Input data2 LUT 3-Input LUT Carry-Out Counter Mode Carry-In (1) (2) data1 3-Input (2) ...
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Normal Mode The normal mode is suitable for general logic applications, combinatorial functions, or wide decoding functions that can take advantage of a cascade chain. In normal mode, four data inputs from the LAB local interconnect and the carry-in are ...
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FLEX 6000 Programmable Logic Device Family Data Sheet Either the counter enable or the up/down control may be used for a given counter. Moreover, the synchronous load can be used as a count enable by routing the register output into ...
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Figure 8. LE Clear & Preset Modes Asynchronous Clear Chip-Wide Reset Asynchronous Clear The flipflop can be cleared by either LABCTRL1 or LABCTRL2. Asynchronous Preset An asynchronous preset is implemented with an asynchronous clear. The Altera software provides preset control ...
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... To/From 10 Adjacent LAB 5 10 through 10 Local Interconnect (32 Channels) Note: (1) For EPF6010A, EPF6016, and EPF6016A devices 144 channels and channels; for EPF6024A devices 186 channels and channels ...
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A row channel can be driven one of two column channels. These three signals feed a 3-to-1 multiplexer that connects to six specific row channels. Row channels drive into the local interconnect via multiplexers. Each ...
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FLEX 6000 Programmable Logic Device Family Data Sheet Figure 10. LAB Connections to Row & Column Interconnects At each intersection, four row channels can drive column channels. Each local channel driven can drive four row channels. Row ...
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... Table 5 each FLEX 6000 device. Table 5. FLEX 6000 FastTrack Interconnect Resources Device EPF6010A EPF6016 EPF6016A EPF6024A In addition to general-purpose I/O pins, FLEX 6000 devices have four dedicated input pins that provide low-skew signal distribution across the device. These four inputs can be used for global clock and asynchronous clear control signals ...
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... LAB D1 Notes: (1) The global clock and clear distribution signals are shown for EPF6016 and EPF6016A devices. In EPF6010A devices, LABs in rows B and C drive global signals. In EPF6024A devices, LABs in rows C and E drive global signals. (2) The local interconnect from LABs C1 and D1 can drive two global control signals on the left side. ...
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I/O Elements An IOE contains a bidirectional I/O buffer and a tri-state buffer. IOEs can be used as input, output, or bidirectional pins. An IOE receives its data signals from the adjacent local interconnect, which can be driven by a ...
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FLEX 6000 Programmable Logic Device Family Data Sheet Each IOE drives a row or column interconnect when used as an input or bidirectional pin. A row IOE can drive up to six row lines; a column IOE can drive up ...
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Figure 14. IOE Connection to Column Interconnect FastFLEX I/ can drive a pin through a local interconnect for faster clock-to-output times. Any LE can drive a pin through the row and local interconnect. Row Interconnect SameFrame 3.3-V FLEX ...
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FLEX 6000 Programmable Logic Device Family Data Sheet Figure 15. SameFrame Pin-Out Example 100-Pin FineLine BGA Package Table 6 feature. Table 6. 3.3-V FLEX 6000 Devices with SameFrame Pin-Outs EPF6016A EPF6024A Output This section discusses slew-rate control, the MultiVolt I/O ...
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MultiVolt I/O Interface The FLEX 6000 device architecture supports the MultiVolt I/O interface feature, which allows FLEX 6000 devices to interface with systems of differing supply voltages. The EPF6016 device can be set for 3.3-V or 5.0-V I/O pin operation. ...
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FLEX 6000 Programmable Logic Device Family Data Sheet Open-drain output pins on 5.0-V or 3.3-V FLEX 6000 devices (with a pull- up resistor to the 5.0-V supply) can drive 5.0-V CMOS input pins that require a V When the pin ...
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... TCK TDO Signal to Be Captured Signal to Be Driven Table 10 devices. Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet Device EPF6010A EPF6016 EPF6016A EPF6024A for more information. shows the timing requirements for the JTAG signals. t JCP JCH JCL JPSU ...
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FLEX 6000 Programmable Logic Device Family Data Sheet Table 10. JTAG Timing Parameters & Values Symbol t JCP t JCH t JCL t JPSU t JPH t JPCO t JPZX t JPXZ t JSSU t JSH t JSCO t JSZX ...
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Operating Tables 11 recommended operating conditions, operating conditions, and Conditions capacitance for 5.0-V and 3.3-V FLEX 6000 devices. Table 11. FLEX 6000 5.0-V Device Absolute Maximum Ratings Symbol Parameter V Supply voltage input voltage ...
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FLEX 6000 Programmable Logic Device Family Data Sheet Table 13. FLEX 6000 5.0-V Device DC Operating Conditions Symbol Parameter V High-level input voltage IH V Low-level input voltage IL V 5.0-V high-level TTL output OH voltage 3.3-V high-level TTL output ...
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Table 15. FLEX 6000 3.3-V Device Absolute Maximum Ratings Symbol Parameter V Supply voltage input voltage output current, per pin OUT T Storage temperature STG T Ambient temperature AMB T Junction temperature J Table ...
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FLEX 6000 Programmable Logic Device Family Data Sheet Table 17. FLEX 6000 3.3-V Device DC Operating Conditions Symbol Parameter V High-level input voltage IH V Low-level input voltage IL V 3.3-V high-level TTL output OH voltage 3.3-V high-level CMOS output ...
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... V on EPF6016 devices, the output driver is compliant with the CCIO PCI Local Bus Specification, Revision 2.2 for 5.0-V operation. When the EPF6010A and EPF6016A devices, the output driver CCIO is compliant with the PCI Local Bus Specification, Revision 2.2 for 3.3-V operation. Figure 18. Output Drive Characteristics ...
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FLEX 6000 Programmable Logic Device Family Data Sheet Timing Model The continuous, high-performance FastTrack Interconnect routing resources ensure predictable performance and accurate simulation and timing analysis. This predictable performance contrasts with that of FPGAs, which use a segmented connection scheme ...
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Figure 19. FLEX 6000 Timing Model Carry-In from Previous LE t REG_TO_REG t CASC_TO_REG t t LOCAL CARRY_TO_REG t DATA_TO_REG LD_CLR t CARRY_TO_CARRY t REG_TO_CARRY t DATA_TO_CARRY t t LABCARRY DIN_D t DIN_C Carry-out to Next LE ...
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FLEX 6000 Programmable Logic Device Family Data Sheet Tables 19 microparameters, which are expressed as worst-case values. Using hand calculations, these parameters can be used to estimate design performance. However, before committing designs to silicon, actual worst-case performance should be ...
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Table 20. IOE Timing Microparameters Symbol t Output buffer and pad delay, slow slew rate = off, V OD1 t Output buffer and pad delay, slow slew rate = off, V OD2 t Output buffer and pad delay, slow slew ...
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... There are 12 LEs, including source and destination registers. The row and column interconnects between the registers vary in length. (7) This timing parameter is shown for reference and is specified by characterization. (8) This timing parameter is specified by characterization. Tables 24 EPF6016A devices. Table 24. LE Timing Microparameters for EPF6010A & EPF6016A Devices (Part Parameter -1 Min Max t REG_TO_REG t ...
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... Table 24. LE Timing Microparameters for EPF6010A & EPF6016A Devices (Part Parameter -1 Min Max CLR LD_CLR t CARRY_TO_CARRY t REG_TO_CARRY t DATA_TO_CARRY t CARRY_TO_CASC t CASC_TO_CASC t REG_TO_CASC t DATA_TO_CASC t 2 2.5 CL Table 25. IOE Timing Microparameters for EPF6010A & EPF6016A Devices Parameter -1 Min Max t OD1 t OD2 ...
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... Parameter -1 Min Max t LOCAL t ROW t COL t DIN_D t DIN_C t LEGLOBAL t LABCARRY t LABCASC Table 27. External Reference Timing Parameters for EPF6010A & EPF6016A Devices Parameter Device Min t EPF6010A 1 EPF6016A Table 28. External Timing Parameters for EPF6010A & EPF6016A Devices Parameter -1 Min Max t 2.1 (1) INSU t 0.2 (2) ...
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Tables 29 Table 29. LE Timing Microparameters for EPF6016 Devices Parameter Min t REG_TO_REG t CASC_TO_REG t CARRY_TO_REG t DATA_TO_REG t CASC_TO_OUT t CARRY_TO_OUT t DATA_TO_OUT t REG_TO_OUT CLR t C ...
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FLEX 6000 Programmable Logic Device Family Data Sheet Table 30. IOE Timing Microparameters for EPF6016 Devices Parameter Min t OD3 ZX1 t ZX2 t ZX3 t IOE IN_DELAY Table 31. Interconnect Timing Microparameters for ...
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Table 33. External Timing Parameters for EPF6016 Devices Parameter Min t 3.2 INSU t 0.0 INH t 2.0 OUTCO Tables 34 Table 34. LE Timing Microparameters for EPF6024A Devices Parameter -1 Min Max t REG_TO_REG t CASC_TO_REG t CARRY_TO_REG t ...
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FLEX 6000 Programmable Logic Device Family Data Sheet Table 35. IOE Timing Microparameters for EPF6024A Devices Parameter -1 Min Max t OD1 t OD2 t OD3 XZ1 t XZ2 t XZ3 t IOE IN_DELAY ...
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... K × f × N × tog × ---------------------------- - MAX LC MHz = Maximum operating frequency in MHz = Total number of LEs used in a FLEX 6000 device = Average percentage of LEs toggling at each clock (typically 12.5%) = Constant, shown in Table 39 Device EPF6010A EPF6016 EPF6016A EPF6024A Unit -3 Min Max 2.6 (1) ns 0.3 (2) ns 2.0 9 the “ ...
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... LEs drive only one short interconnect segment. This assumption may lead to inaccurate results, compared to measured power consumption for an actual design in a segmented interconnect FPGA. Figure 20 frequency for EPF6010A, EPF6016, EPF6016A, and EPF6024A devices. 48 estimate based on typical conditions with CC should be verified during operation ...
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... Figure 20. I vs. Operating Frequency CCACTIVE EPF6010A 200 150 I Supply CC Current 100 (mA Frequency (MHz) EPF6016A 250 200 I Supply CC 150 Current (mA) 100 Frequency (MHz) Device The FLEX 6000 architecture supports several configuration schemes to load a design into the device(s) on the circuit board. This section Configuration & ...
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FLEX 6000 Programmable Logic Device Family Data Sheet Operating Modes The FLEX 6000 architecture uses SRAM configuration elements that require configuration data to be loaded every time the circuit powers up. This process of physically loading the SRAM data into ...
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Device Pin- See the Altera web site (http://www.altera.com) or the Altera Digital Library for pin-out information. Outs Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet 51 ...
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FLEX 6000 Programmable Logic Device Family Data Sheet Altera, BitBlaster, ByteBlasterMV, FastFlex, FastTrack, FineLine BGA, FLEX, MasterBlaster, MAX+PLUS II, MegaCore, MultiVolt, OptiFLEX, Quartus, SameFrame, and specific device designations are trademarks and/or service marks of Altera Corporation in the United States ...