CA3318CE Intersil, CA3318CE Datasheet - Page 7

• Manufacturer Part Number: CA3318CE
• Description: 8 BIT "FLASH" A/D
• Manufacturer: Intersil

Specifications of CA3318CE

• Rohs Status: RoHS non-compliant
• Other names: CA3318

Typical Performance Curves
Pin Descriptions
PIN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
PHASE
NAME
V
V
V
1
V
1
3
V
CE2
CE1
CLK
V
REF
REF
V
V
OF
/
/
/
B1
B2
B3
B4
B5
B6
B7
B8
AA
AA
4
2
4
SS
DD
IN
IN
R
R
R
+
-
+
-
Bit 1 (LSB)
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8 (MSB)
Overflow
Reference Ladder
Digital Ground
Digital Power Supply, +5V
Three-State Output Enable Input,
Active Low, See Truth Table.
Three-State Output Enable Input
Active High. See Truth Table.
Reference Voltage Negative Input
Analog Signal Input
Analog Ground
Clock Input
Sample clock phase control input.
When PHASE is low, “Sample
Unknown” occurs when the clock is
low and “Auto Balance” occurs when
the clock is high (see text).
Reference Ladder Midpoint
Analog Signal Input
Reference Voltage Positive Input
Reference Ladder
Analog Power Supply, +5V
DESCRIPTION
8.0
7.6
7.2
6.8
6.4
6.0
5.6
5.2
4.8
4.4
4.0
0.0
FIGURE 10. ENOB vs INPUT FREQUENCY
1
3
Output Data Bits
(Continued)
/
/
0.5
(High = True)
4
4
Point
Point
f
S
1.0
= 15MHz
1.5
CA3318
2.0
7
f
I
(MHz)
converter to obtain its high speed operation. The sequence
conversion takes one clock cycle (see Note). With the phase
2.5
X = Don’t Care
Theory of Operation
A sequential parallel technique is used by the CA3318
consists of the “Auto-Balance” phase, φ1, and the “Sample
Unknown” phase, φ2. (Refer to the circuit diagram.) Each
control (pin 19) high, the “Auto-Balance” (φ1) occurs during
the high period of the clock cycle, and the “Sample Unknown”
(φ2) occurs during the low period of the clock cycle.
NOTE: The device requires only a single phase clock The terminology
of φ1 and φ2 refers to the high and low periods of the same clock.
During the “Auto-Balance” phase, a transmission switch is
used to connect each of the first set of 256 commutating
capacitors to their associated ladder reference tap. Those
tap voltages will be as follows:
Where:
V
V
N
The other side of these capacitors are connected to single-
stage amplifiers whose outputs are shorted to their inputs by
switches. This balances the amplifiers at their intrinsic trip
points, which is approximately (V
of capacitors now charges to their associated tap voltages.
V
TAP
REF
TAP
3.0
CE1
(n) = reference ladder tap voltage at point n,
(N) = [(N/256) V
0
1
X
3.5
= [(2N - 1)/512] V
= voltage across V
= tap number (1 through 256).
4.0
CHIP ENABLE TRUTH TABLE
4.5
CE2
1
1
0
REF
5.0
] - (1/512) V
REF
REF
,
Three-State
Three-State
AA
- to V
B1 - B8
Valid
+ - V
REF
REF
AA
]
+,
-)/2. The first set
Three-State
Valid
Valid
OF