CLC5958PCASM National Semiconductor, CLC5958PCASM Datasheet - Page 2

• Manufacturer Part Number: CLC5958PCASM
• Description: EVALUATION BOARD FOR CLC5958
• Manufacturer: National Semiconductor

Specifications of CLC5958PCASM

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CLC5958PCASM

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A
A
ENCODE,
ENCODE
D0–D13
DAV
V
GND
V
DV
Pin Configuration
Pin Descriptions
IN
IN
CM
CC
Pin Name
CC
,
1–4, 8, 11, 12, 15, 19, 20, 23–26, 35,
36, 47, 48 and vias
5–7, 16–18, 22, 46
Pin No.
28–34,
13, 14
39–45
37, 38
9, 10
27
21
01501902
Differential inputs. Self biased at a common mode voltage of
+3.25V. The ADC full scale input is 2.048 V
Differential clock inputs. ENCODE initiates a new data conversion
cycle on each rising edge. Clock signals may be sinusoidal or
square waves with PECL encode levels. The falling edge of
ENCODE clocks internal pipeline stages.
Digital data outputs. CMOS and TTL compatible. D0 is the LSB and
D13 is the inverted MSB. Output coding is two’s complement.
Data valid. The rising edge of this signal occurs when output data is
valid and may be used to latch data into following circuitry.
Internal analog input common mode voltage reference. Nominally
+3.25V. Can be used to establish the analog input common mode
voltage for DC coupled applications (DC coupling not
recommended, see applications section).
Circuit ground.
+5V power supply. Bypass each group of supply pins to ground with
a 0.01 µF capacitor.
+3.3V to +5V power supply for the digital outputs. Establishes the
high output level for the digital outputs. Bypass to ground with a
0.1 µF capacitor.
2
Ordering Information
CLC5958SLB
CLC5958PCASM
Description
48-Pin CSP
Evaluation Board
PP
differential.