EVAL-AD7684CB Analog Devices Inc, EVAL-AD7684CB Datasheet - Page 12

• Manufacturer Part Number: EVAL-AD7684CB
• Description: BOARD EVAL FOR AD7684 PCB
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7684CB

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 100k
• Data Interface: Serial
• Inputs Per Adc: 2 Single
• Input Range: ±VREF
• Power (typ) @ Conditions: 4mW @ 5 V, 100kSPS
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7684
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD7684
APPLICATION INFORMATION
CIRCUIT INFORMATION
The AD7684 is a low power, single-supply, 16-bit ADC using a
successive approximation architecture. It is capable of converting
100,000 samples per second (100 kSPS) and powers down
between conversions. When operating at 10 kSPS, for example,
it consumes typically 150 μW with a 2.7 V supply, ideal for
battery-powered applications.
The AD7684 provides the user with an on-chip, track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple, multiplexed channel applications.
The AD7684 is specified from 2.7 V to 5.5 V. It is housed in an
8-lead MSOP.
CONVERTER OPERATION
The AD7684 is a successive approximation ADC based on a
charge redistribution DAC. Figure 20 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary-weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
input of the comparator are connected to GND via SW+ and
SW−. All independent switches are connected to the analog
inputs. Therefore, the capacitor arrays are used as sampling
capacitors and acquire the analog signal on the +IN and −IN
inputs. When the acquisition phase is complete and the CS
input goes low, a conversion phase is initiated. When the
conversion phase begins, SW+ and SW− are opened first. The
two capacitor arrays are then disconnected from the inputs and
connected to the GND input. Therefore, the differential voltage
between the inputs, +IN and −IN, captured at the end of the
acquisition phase is applied to the comparator inputs, causing
the comparator to become unbalanced. By switching each
element of the capacitor array between GND and REF, the
comparator input varies by binary-weighted voltage steps
(V
switches, starting with the MSB, to bring the comparator back
REF
/2, V
REF
GND
REF
+IN
–IN
/4...V
REF
/65,536). The control logic toggles these
32,768C
32,768C
16,384C
16,384C
MSB
MSB
Figure 20. ADC Simplified Schematic
4C
4C
Rev. A | Page 12 of 16
2C
2C
C
C
into a balanced condition. After the completion of this process,
the part returns to the acquisition phase and the control logic
generates the ADC output code.
TRANSFER FUNCTIONS
The ideal transfer function for the AD7684 is shown in
Figure 21 and Table 8.
Table 8. Output Codes and Ideal Input Voltages
Description
FSR − 1 LSB
Midscale + 1 LSB
Midscale
Midscale – 1 LSB
−FSR + 1 LSB
−FSR
1
2
This is also the code for an overranged analog input (V
V
This is also the code for an underranged analog input (V
−V
REF
REF
− V
+ V
C
C
GND
011...111
011...110
011...101
100...010
100...001
100...000
GND
LSB
LSB
).
).
–FSR
–FSR + 0.5 LSB
SW+
SW–
Figure 21. ADC Ideal Transfer Function
COMP
Analog Input
V
+4.999847 V
+152.6 μV
0 V
−152.6 μV
−4.999847 V
−5 V
–FSR + 1 LSB
SWITCHES CONTROL
REF
= 5 V
CONTROL
LOGIC
CNV
ANALOG INPUT
Digital Output Code Hex
7FFF
0001
0000
FFFF
8001
8000
BUSY
+FSR – 1.5 LSB
OUTPUT CODE
1
2
+IN
+FSR – 1 LSB
+IN
− V
− V
−IN
−IN
above
below